HD64F2149YV datasheet(779/1075 Pages) RENESAS

779 / 1075 page

Section 24 Power-Down State

Rev. 3.00 Jan 18, 2006 page 751 of 1044

REJ09B0280-0300

24.1.1

The power-down state is controlled by the SBYCR, LPWRCR, TCSR (WDT1), and MSTPCR

registers. Table 24.3 summarizes these registers.

Table 24.3

Power-Down State Registers

Name

Abbreviation

R/W

Initial Value

Address*

Standby control register

SBYCR

R/W

H'00

H'FF84*

Low-power control register

LPWRCR

R/W

H'00

H'FF85*

Timer control/status register

(WDT1)

TCSR

R/W

H'00

H'FFEA

Module stop control register

MSTPCRH

R/W

H'3F

H'FF86*

MSTPCRL

R/W

H'FF

H'FF87*

Notes: 1. Lower 16 bits of the address.

2. A CPU access to some of the control registers in the power-down state is controlled by

the FLSHE bit of the serial/timer control register (STCR).

24.2

24.2.1

Standby Control Register (SBYCR)

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

—

SCK0

R/W

SCK2

R/W

SCK1

R/W

Bit

Initial value

Read/Write

SBYCR is an 8-bit readable/writable register that performs power-down mode control.

SBYCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Software Standby (SSBY): Determines the operating mode, in combination with other

control bits, when a power-down mode transition is made by executing a SLEEP instruction. The

SSBY setting is not changed by a mode transition due to an interrupt, etc.

HD64F2149YV Folha de dados(PDF) 779 Page - Renesas Technology Corp

HD64F2149YV Folha de dados(HTML) 779 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL