HD64F2149YV datasheet(764/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 23 Clock Pulse Generator

Rev. 3.00 Jan 18, 2006 page 736 of 1044

REJ09B0280-0300

23.1.2

The clock pulse generator is controlled by the standby control register (SBYCR) and low-power

control register (LPWRCR). Table 23.1 shows the register configuration.

Table 23.1

CPG Registers

Name

Abbreviation

R/W

Initial Value

Address*

Standby control register

SBYCR

R/W

H'00

H'FF84

Low-power control register

LPWRCR

R/W

H'00

H'FF85

Note:

Lower 16 bits of the address.

23.2

23.2.1

Standby Control Register (SBYCR)

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

—

SCK0

R/W

SCK2

R/W

SCK1

R/W

Bit

Initial value

Read/Write

SBYCR is an 8-bit readable/writable register that performs power-down mode control.

Only bits 0 to 2 are described here. For a description of the other bits, see section 24.2.1, Standby

Control Register (SBYCR).

SBYCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock

for high-speed mode and medium-speed mode.

When operating the device after a transition to subactive mode or watch mode bits SCK2 to SCK0

should all be cleared to 0.

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