HD64F2149YV datasheet(765/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 23 Clock Pulse Generator

Rev. 3.00 Jan 18, 2006 page 737 of 1044

REJ09B0280-0300

Bit 2

Bit 1

Bit 0

SCK2

SCK1

SCK0

Description

Bus master is in high-speed mode

(Initial value)

Medium-speed clock is

φ/2

Medium-speed clock is

φ/4

Medium-speed clock is

φ/8

Medium-speed clock is

φ/16

Medium-speed clock is

φ/32

1—

—

23.2.2

Low-Power Control Register (LPWRCR)

DTON

R/W

LSON

R/W

NESEL

R/W

EXCLE

R/W

—

R/W

—

Bit

Initial value

Read/Write

(H8S/2169)

Read/Write

(H8S/2149)

LPWRCR is an 8-bit readable/writable register that performs power-down mode control.

Only bit 4 is described here. For a description of the other bits, see section 24.2.2, Low-Power

Control Register (LPWRCR).

LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 4—Subclock Input Enable (EXCLE): Controls subclock input from the EXCL pin.

Bit 4

EXCLE

Description

Subclock input from EXCL pin is disabled

(Initial value)

Subclock input from EXCL pin is enabled

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