HD64F2149YV datasheet(741/1075 Pages) RENESAS

741 / 1075 page

Section 22 ROM

Rev. 3.00 Jan 18, 2006 page 713 of 1044

REJ09B0280-0300

Start

End of programming

End sub

Set SWE bit in FLMCR1

Wait (x)

µs

n = 1

m = 0

Sub-routine-call

See Note 7 for pulse width

Note 7: Write Pulse Width

Start of programming

Sub-routine write pulse

Set PSU bit in FLMCR2

Enable WDT

Set P bit in FLMCR1

Wait (y)

µs

Clear P bit in FLMCR1

Wait (z1)

µs, (z2) µs or (z3) µs

Clear PSU bit in FLMCR2

Wait (

α) µs

Disable WDT

Wait (

β) µs

Write pulse application subroutine

Wait (

γ) µs

Wait (

ε) µs

*5 *6

Wait (

η) µs

Set PV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Program data =

verify data?

Transfer additional program data

to additional program data area

Additional program data computation

Clear PV bit in FLMCR1

Clear SWE bit in FLMCR1

m = 1

End of 128-byte

data verification?

m = 0?

Increment

address

Programming failure

Comments

Write 128-byte data in RAM reprogram data

area consecutively to flash memory

Write pulse

(z1)

µs or (z2) µs

RAM

Program data storage

area (128 bytes)

Reprogram data storage

area (128 bytes)

Store 128-byte program data in program

data area and reprogram data area

Number of Writes n

...

998

999

1000

Write Time (z)

µs

...

Reprogram data computation

Transfer reprogram data to reprogram data area *4

≥ n?

Write 128-byte data in additional program data

area in RAM consecutively to flash memory

Additional write pulse (z3)

µs

Wait (

θ) µs

Note: Use a (z3)

µs write pulse for additional

programming.

Program Data Computation Chart

Additional program data

storage area (128 bytes)

Perform programming in the erased state.

Do not perform additional programming

on previously programmed addresses.

← n + 1

≥ 1000?

Clear SWE bit in FLMCR1

Wait (

θ) µs

≥ n?

Notes: 1. Data transfer is performed by byte transfer.

The lower 8 bits of the first address written to must be

H'00 or H'80. A 128-byte data transfer must be performed

even if writing fewer than 128 bytes; in this case,

H'FF data must be written to the extra addresses.

2. Verify data is read in 16-bit (word) units.

3. Even bits for which programming has been

completed in the 128-byte programming loop will be

subjected to additional programming if they fail

the subsequent verify operation.

4. A 128-byte area for storing program data, a 128-byte area

for storing reprogram data, and a 128-byte area for storing additional program data must be provided in RAM.

The reprogram and additional program data contents are modified as programming proceeds.

5. The write pulse of (z1)

µs or (z2) µs is applied according to the progress of the programming operation. See Note 7 for the pulse widths. When writing of additional

program data is executed, a (z3) µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.

6. See section 25.6, Flash Memory Characteristics, for the values of x, y, z1, z2, z3,

α, β, γ, ε, η, θ, and N.

Programming completed

Programming incomplete; reprogram

Still in erased state; no action

Original Dat

(D)

Verify Data

(V)

Reprogram Data

(X)

Comments

Additional Program Data Computation Chart

Additional programming executed

Additional programming not executed

Reprogram Data

(X')

Verify Data

(V)

Additional Program

Data (Y)

Figure 22.12 Program/Program-Verify Flowchart

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