HD64F2149YV datasheet(739/1075 Pages) RENESAS

739 / 1075 page

Section 22 ROM

Rev. 3.00 Jan 18, 2006 page 711 of 1044

REJ09B0280-0300

22.7.1

Program Mode

Follow the procedure shown in the program/program-verify flowchart in figure 22.12 to write data

or programs to flash memory. Performing program operations according to this flowchart will

enable data or programs to be written to flash memory without subjecting the device to voltage

stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a

time.

The wait times (x, y, z1, z2, z3,

α, ß, γ, ε, η, θ) after setting/clearing individual bits in flash

memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of writes (N)

are shown in section 25.6, Flash Memory Characteristics.

Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control

data area, and the 128-byte data in the reprogram data area written consecutively to the write

addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive

byte data transfers are performed. The program address and program data are latched in the flash

memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this

case, H'FF data must be written to the extra addresses.

Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.

Set a value greater than (y + z2 +

α + β) µs as the WDT overflow period. After this, preparation

for program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the

elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in

FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a

program setting so that the time for one programming operation is within the range of (z1), (z2) or

(z3) µs.

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