HD64F2149YV datasheet(704/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 20 A/D Converter

Rev. 3.00 Jan 18, 2006 page 676 of 1044

REJ09B0280-0300

20.4.3

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input at a time t

D after the ADST bit is set to 1, then starts conversion. Figure 20.5 shows the A/D

conversion timing. Table 20.4 indicates the A/D conversion time.

As indicated in figure 20.5, the A/D conversion time includes t

D and the input sampling time. The

length of t

D varies depending on the timing of the write access to ADCSR. The total conversion

time therefore varies within the ranges indicated in table 20.4.

In scan mode, the values given in table 20.4 apply to the first conversion time. In the second and

subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states

when CKS = 1.

(1)

(2)

SPL

CONV

Input sampling

timing

ADF

Address

Write signal

Legend:

(1):

ADCSR write cycle

(2):

ADCSR address

tD:

A/D conversion start delay

tSPL:

Input sampling time

tCONV: A/D conversion time

Figure 20.5 A/D Conversion Timing

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