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HD64F2149YV Folha de dados(PDF) 706 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 706 Page - Renesas Technology Corp |
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706 / 1075 page ![]() Section 20 A/D Converter Rev. 3.00 Jan 18, 2006 page 678 of 1044 REJ09B0280-0300 20.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: 1. Analog input voltage range The voltage applied to the ANn analog input pins during A/D conversion should be in the range AVSS ≤ ANn ≤ AVref (n = 0 to 7). 2. Digital input voltage range The voltage applied to the CINn digital input pins should be in the range AVSS ≤ CINn ≤ AVref and VSS ≤ CINn ≤ VCC (n = 0 to 15). 3. Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. 4. Setting Range of AVref Pin: The reference voltage supplied via the AVref pin should be in the range AVref ≤ AVCC. If conditions 1 to 4 above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference power supply (AVref), and analog power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) or analog reference power supply pin (AVref) should be connected between AVCC and AVSS as shown in figure 20.7. Also, the bypass capacitors connected to AVCC, AVref and the filter capacitor connected to AN0 to AN7 must be connected to AVSS. |
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