HD64F2149YV datasheet(705/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 20 A/D Converter

Rev. 3.00 Jan 18, 2006 page 677 of 1044

REJ09B0280-0300

Table 20.4

A/D Conversion Time (Single Mode)

CKS = 0

CKS = 1

Item

Symbol

Min

Typ

Max

Min

Typ

Max

A/D conversion start delay

—

Input sampling time

SPL

—

——

—

A/D conversion time

CONV

259

—

266

131

—

134

Note:

Values in the table are the number of states.

20.4.4

External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in

ADCR, external trigger input is enabled at the

ADTRG pin. A falling edge at the ADTRG pin sets

the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan

modes, are the same as when the ADST bit is set to 1 by software. Figure 20.6 shows the timing.

ADTRG

Internal trigger signal

ADST

A/D conversion

Figure 20.6 External Trigger Input Timing

20.5

Interrupts

The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt

request can be enabled or disabled by the ADIE bit in ADCSR.

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