HD64F2149YV datasheet(631/1075 Pages) RENESAS

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 603 of 1044

REJ09B0280-0300

Section 18B Host Interface

LPC Interface (LPC)

18B.1

Overview

The H8S/2169 or H8S/2149 has an on-chip host interface (HIF) that can be connected to the ISA

bus (X-BUS) widely used as the internal bus in personal computers. In addition, the H8S/2169 or

H8S/2149 has an on-chip LPC interface, a new host interface replacing the ISA bus. In the

following text, these two host interfaces (HIFs) are referred to as XBS and LPC, respectively.

The HIF:LPC performs serial transfer of cycle type, address, and data, synchronized with the 33

MHz PCI clock. It uses four signal lines for address/data, and one for host interrupt requests.

Various kinds of cycle are available for the LPC interface, but the chip’s HIF:LPC supports only

I/O read cycle and I/O write cycle transfers.

The HIF:LPC consists of three register sets comprising data and status registers, plus a control

down functions that can control the PCI clock and shut down the host interface.

The HIF:LPC ia available only in single-chip mode.

18B.1.1 Features

The features of the HIF:LPC are summarized below.

• Supports LPC interface I/O read cycles and I/O write cycles

 Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.

 Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME).

• Has three register sets comprising data and status registers

 The basic register set comprises three bytes: an input register (IDR), output register (ODR),

and status register (STR).

 Channels 1 and 2 have fixed I/O addresses of H'60/H'64 and H'62/H'66, respectively,

enabling the same functions to be implemented as on HIF:XBS channels 1 and 2.

 A fast A20 gate function is also provided.

 The I/O address can be set for channel 3. Sixteen two-way register bytes can be

manipulated in addition to the basic register set.

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