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HD64F2149YV Folha de dados(PDF) 557 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 557 Page - Renesas Technology Corp |
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557 / 1075 page ![]() Section 16 I 2C Bus Interface Rev. 3.00 Jan 18, 2006 page 529 of 1044 REJ09B0280-0300 SDA (Master output) SDA (Slave output) 2 1 4 3 6 5 8 7 1 234 5 9 9 A A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 IRIC IRTR ICDR SCL (Master output) Master transmit mode Master receive mode Data 1 Data 1 Data 2 [2] ICDR read (dummy read) [1] TRS = 0 clear WAIT = 1 set ACKB = 0 clear [2] IRIC clear [7] IRIC clear [6] ICDR read (Data 1) [4] IRIC clear User processing [5] [3] Figure 16.8 (1) Example of Master Receive Mode Operating Timing (MLS = ACKB = 0 and WAIT = 1) SDA (Master output) SDA (Slave output) 2 1 4 3 6 5 8 7 1 2 9 9 8 A A Bit 7 Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 IRIC IRTR ICDR SCL (Master output) Data 3 Data 2 Data 1 Data 2 Data 3 Data 4 [9] IRIC clear [7] IRIC clear [9] IRIC clear [7] IRIC clear User processing [5] [8] [5] [8] [6] ICDR read (Data 2) [6] ICDR read (Data 3) Figure 16.8 (2) Example of Master Receive Mode Operating Timing (MLS = ACKB = 0 and WAIT = 1) |
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