HD64F2149YV datasheet(561/1075 Pages) RENESAS

561 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 533 of 1044

REJ09B0280-0300

[3] After clearing the IRIC flag to 0, write data to ICDR. The TDRE internal flag is cleared to 0.

The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR

flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. The

slave device sequentially sends the data written into ICDR in accordance with the clock output

by the master device at the timing shown in figure 16.10.

[4] When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of

the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, this slave device

drives SCL low from the fall of the transmit clock until data is written to ICDR. The master

device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this

acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine

whether the transfer operation was performed normally. When the TDRE internal flag is 0, the

data written into ICDR is transferred to ICDRS, transmission is started, and the TDRE internal

flag and the IRIC and IRTR flags are set to 1 again.

[5] To continue transmission, clear the IRIC flag to 0, then write the next data to be transmitted

into ICDR. The TDRE flag is cleared to 0.

Transmit operations can be performed continuously by repeating steps [4] and [5]. To end

transmission, write H'FF to ICDR to release SDA on the slave side. When SDA is changed from

low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is

cleared to 0.

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