HD64F2149YV datasheet(556/1075 Pages) RENESAS

556 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 528 of 1044

REJ09B0280-0300

[3] The IRIC flag is set to 1 at the fall of the 8th clock of a one-frame reception clock. At this

point, if the IEIC bit of ICCR is set to 1, an interrupt request is generated to the CPU.

SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag

is cleared. If the first frame is the final reception frame, execute the end processing as

described in [10].

[4] Clear the IRIC flag to 0 to release from the wait state.

The master device outputs the 9th receive clock pulse, sets SDA to low, and returns an

acknowledge signal.

[5] When one frame of data has been transmitted, the IRIC and IRTR flags are set to 1 at the rise

of the 9th transmit clock pulse.

The master device continues to output the receive clock for the next receive data.

[6] Read the ICDR receive data.

[7] Clear the IRIC flag to indicate the next wait.

From clearing of the IRIC flag to completion of data transmission as described in steps [5],

[6], and [7], must be performed within the time taken to transfer one byte because releasing

of the wait state as described in step [4](or[9]).

[8] The IRIC flag is set to 1 at the fall of the 8th receive clock pulse.

SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag

is cleared.

If this frame is the final reception frame, execute the end processing as described in [10].

[9] Clear the IRIC flag to 0 to release from the wait state.

The master device outputs the 9th reception clock pulse, sets SDA to low, and returns an

acknowledge signal.

By repeating steps [5] to [9] above, more data can be received.

[10] Set the ACKB bit of ICSR to 1 and set the acknowledge data for the final reception.

Set the TRS bit of ICCR to 1 to change receive mode to transmit mode.

[11] Clear the IRIC flag to release from the wait state.

[12] When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th

reception clock pulse.

[13] Clear the WAIT bit of ICMR to 0 to cancel wait mode. Read the ICDR receive data and clear

the IRIC flag to 0.

Clear the IRIC flag only when WAIT = 0.

(If the stop-condition generation command is executed after clearing the IRIC flag to 0 and

then clearing the WAIT bit to 0, the SDA line is fixed low and the stop condition cannot be

generated.)

[14] Write 0 to BBSY and SCP. This changes SDA from low to high when SCL is high, and

generates the stop condition.

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