HD64F2149YV datasheet(555/1075 Pages) RENESAS

555 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 527 of 1044

REJ09B0280-0300

SDA

(Master output)

SDA

(Slave output)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 7

Bit 6

IRIC

IRTR

ICDR

Normal

operation

Precaution:

Data set timing to

ICDR

Incorrect operation

SCL

(Master output)

Start condition generation

Slave address

Data 1

[9] ICDR write

[9] IRIC clear

[6] ICDR write

[6] IRIC clear

[4] Write 1 to BBSY

and 0 to SCP

(start condition

issuance)

User processing

Address + R/

[7]

[5]

(ICDR writing

prohibited)

Figure 16.7 Example of Master Transmit Mode Operating Timing (MLS = WAIT = 0)

16.3.3

Master Receive Operation

In master receive mode, the master device outputs the receive clock, receives data, and returns an

acknowledge signal. The slave device transmits data.

The receive procedure and operations by which data is sequentially received in synchronization

with ICDR read operations, are described below.

[1] Clear the TRS bit of ICCR to 0 and switch from transmit mode to receive mode. Set the

WAIT bit to 1 and clear the ACKB bit of ICSR to 0 (acknowledge data setting).

[2] When ICDR is read (dummy data read), reception is started and the receive clock is output,

and data is received, in synchronization with the internal clock. To indicate the wait, clear

the IRIC flag to 0.

Reading from ICDR and clearing of the IRIC flag must be executed continuously so that no

interrupt is inserted.

If a period of time that is equal to transfer one byte has elapsed by the time the IRIC flag is

cleared, the end of transfer cannot be identified.

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