HD64F2149YV datasheet(551/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 523 of 1044

REJ09B0280-0300

MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

MSTPCRL Bit 4—Module Stop (MSTP4): Specifies IIC channel 0 module stop mode.

MSTPCRL

Bit 4

MSTP4

Description

IIC channel 0 module stop mode is cleared

IIC channel 0 module stop mode is set

(Initial value)

MSTPCRL Bit 3—Module Stop (MSTP3): Specifies IIC channel 1 module stop mode.

MSTPCRL

Bit 3

MSTP3

Description

IIC channel 1 module stop mode is cleared

IIC channel 1 module stop mode is set

(Initial value)

16.3

Operation

16.3.1

2C Bus Data Format

The I

2C bus interface has serial and I2C bus formats.

The I

2C bus formats are addressing formats with an acknowledge bit. These are shown in figures

16.3 (a) and (b). The first frame following a start condition always consists of 8 bits.

IIC channel 0 only is capable of formatless operation, as shown in figure 16.4.

The serial format is a non-addressing format with no acknowledge bit. This is shown in figure

16.5.

Figure 16.6 shows the I

2C bus timing.

The symbols used in figures 16.3 to 16.6 are explained in table 16.4.

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