HD64F2149YV datasheet(547/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 519 of 1044

REJ09B0280-0300

16.2.7

Serial/Timer Control Register (STCR)

Bit

Initial value

Read/Write

IICS

R/W

IICX1

R/W

IICX0

R/W

IICE

R/W

FLSHE

R/W

ICKS0

R/W

—

R/W

ICKS1

R/W

STCR is an 8-bit readable/writable register that controls register access, the I

2C interface operating

mode (when the on-chip IIC option is included), and on-chip flash memory, and selects the TCNT

input clock source. For details of functions not related to the I

2C bus interface, see section 3.2.4,

Serial Timer Control Register (STCR), and the descriptions of the relevant modules. If a module

controlled by STCR is not used, do not write 1 to the corresponding bit.

STCR is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—I

2C Extra Buffer Select (IICS): Designates bits 7 to 4 of port A as the same kind of

output buffer as SCL and SDA. This bit is used when implementing the I

2C interface by software

only.

Bit 7

IICS

Description

PA7 to PA4 are normal I/O pins

(Initial value)

PA7 to PA4 are I/O pins with bus driving capability

Bits 6 and 5—I

2C Transfer Select 1 and 0 (IICX1, IICX0): These bits, together with bits CKS2

to CKS0 in ICMR of IIC1, selects the transfer rate in master mode. For details, see section 16.2.4,

2C Bus Mode Register (ICMR).

Bit 4—I

2C Master Enable (IICE): Controls CPU access to the I2C bus interface data and control

registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR).

Bit 4

IICE

Description

CPU access to I

2C bus interface data and control registers is disabled

(Initial value)

CPU access to I

2C bus interface data and control registers is enabled

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