ADIN1111CCPZ-R7 datasheet(8/109 Pages) AD

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Data Sheet

ADIN1111

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 8 of 109

Figure 4. Pin Configuration

Table 7. Pin Function Descriptions (Hardware Pin Configuration Groupings Are Subject to Change)

Pin No.

Mnemonic1

PU/PD2

Description

Clock Interface

CLK25_REF

N/A

Analog Reference Clock Output. The 25 MHz reference clock from the crystal

oscillator is available on the CLK25_REF pin.

XTAL_I/CLK_IN

N/A

Input for Crystal (XTAL_I).

Single-Ended 25 MHz Reference Clock Input (CLK_IN).

XTAL_O

N/A

Crystal Output. If using a single-ended reference clock on XTAL_I/CLK_IN, leave

XTAL_O open circuit. See the External 25 MHz Clock Input section.

SPI

SDI

Serial Data Input. Data is clocked in on the SDI pin on each rising edge.

SDO/SPI_CFG03

Serial Data Output (SDO). Data is clocked out on the SDO pin on each falling edge.

SPI Protocol Configuration Pin 0 (SPI_CFG0). See Table 15.

INT

Interrupt Pin Output. Open-drain, active low output. A low on INT indicates an

unmasked management interrupt. This pin requires a 1.5 kΩ pull-up resistor to VDDIO.

Active Low Chip Select.

SPI_CFG1

SPI Protocol Configuration Pin 1. See Table 15.

SCLK

Serial Clock Input. Data is clocked into the shift register on each rising edge.

Time Stamp Support

TS_TIMER/MS_SEL3

Time Stamp Timer Output (TS_TIMER). See the Applications Information section.

Leader/Follower Selection (MS_SEL). Set high for prefer leader selection or low for

prefer follower selection. See Table 13.

TS_CAPT

Time Stamp Capture, Input to ADIN1111. See the Applications Information section. If

not using the time stamp function, this pin can be left floating because an internal

pull-down resistor is present.

Reset

RESET

Active Low Input. Hold low for >10 μs. RESET does not require a pull-up resistor

because an internal pull-up resistor is present.

Media Dependent Interface

(MDI)

TXN

N/A

Transmit/Receive Negative Pin.

TXP

N/A

Transmit/Receive Positive Pin.

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