ADIN1111CCPZ-R7 datasheet(4/109 Pages) AD

4 / 109 page

Data Sheet

ADIN1111

SPECIFICATIONS

analog.com

Rev. A | 4 of 109

Table 1. (Continued)

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLOCKS

External Crystal (XTAL)

Requirements for external crystal used on the XTAL_I and

XTAL_O pins

Crystal Frequency

MHz

Crystal Frequency Tolerance

−30

+30

ppm

Crystal Drive Level

<200

µW

Crystal Equivalent Series Resistance (ESR)

XTAL_I, XTAL_O Input Capacitance (CIN,EQ)

1.5

Equivalent parallel differential input capacitance looking

into XTAL_x pins

Crystal Load Capacitance (CL)1

Including printed circuit board (PCB) trace capacitance

and XTAL_I, XTAL_O CIN,EQ

Start-Up Time

Crystal oscillator only

Clock Input (CLK_IN)

Clock Input Frequency

MHz

Requirements for external clock applied to XTAL_I pin,

media independent interface (MII) mode

MHz

Reduced media independent interface (RMII) mode

Clock Jitter

RMS

Clock Input Voltage Range

0.8

2.5

V p-p

AC-coupled sine or square wave at XTAL_I pin, see

External 25 MHz Clock Input section for more information

Clock Input Duty Cycle

XTAL_I Input Impedance (ZIN,EQ)

Driving Point Resistance RP2

kΩ

RP||CP

Driving Point Capacitance CP2

CLK25_REF Clock Output

CLK25_REF Frequency

MHz

VOH

1.05

Load 10 pF

VOL

Load 10 pF

CLK25_REF Duty Cycle

Load 10 pF

CLK25_REF Frequency Tolerance

−50

+50

ppm

1 CL = ((C1 × C2)/(C1 + C2) + CSTRAY), where CSTRAY is the stray capacitance including routing and package parasitics.

2 RP and CP are the values of the equivalent parallel RC circuit to ac ground (RP||RC), modeling the driving point impedance of the XTAL_I/CLK_IN pin.

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