ADIN1111CCPZ-R7 datasheet(58/109 Pages) AD

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Data Sheet

ADIN1111

REGISTERS

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Rev. A | 58 of 109

Table 64. Bit Descriptions for TX_SPACE

Bits

Bit Name

Description

Reset

Access

[31:14]

RESERVED

Reserved.

0x0

[13:0]

TX_SPACE

Transmit FIFO Space Available in Half Words (16 Bits). This is used by the host software to determine if there

is space in the Tx FIFO for a frame. Note that the software can queue 2 frames for transmission and wait for

a TX_RDY interrupt, or it can fill the Tx FIFO with multiple frames and use TX_SPACE to determine if there is

space for the next frame. Note that an extra 2 words of space are needed per frame in the host TX FIFO to

store the frame size and header. For example, if the TX_SPACE is 64, the maximum size frame that can be

written is (64 -2) × 2 bytes = 124 bytes. Only used with the generic SPI protocol.

0xFFF

Transmit Threshold Register

Address: 0x34, Reset: 0x00000041, Name: TX_THRESH

Table 65. Bit Descriptions for TX_THRESH

Bits

Bit Name

Description

Reset

Access

[31:6]

RESERVED

Reserved.

0x1

[5:0]

HOST_TX_THRESH

Host Transmit Start Threshold in Cut Through. When cut through on Tx is enabled

(TX_CUT_THRU_EN = 1), this field is used to set the threshold in half words (16 bits) at which

frame transmission starts for frames coming from the host. The range of valid values for this field is

1 to 26 half words.

0x1

R/W

MAC FIFO Clear Register

Address: 0x36, Reset: 0x00000000, Name: FIFO_CLR

Table 66. Bit Descriptions for FIFO_CLR

Bits

Bit Name

Description

Reset

Access

[31:2]

RESERVED

Reserved.

0x0

MAC_TXF_CLR

Clear the Host Transmit FIFO. If a frame is currently being transmitted, the transmission stops and a bad

CRC is appended to the frame.

0x0

MAC_RXF_CLR

Clear the Receive FIFOs. Writes to the Rx FIFO resume at the start of the next frame.

0x0

Scratch Registers

Address: 0x37 to 0x3A (Increments of 1), Reset: 0x00000000, Name: SCRATCHn

Table 67. Bit Descriptions for SCRATCHn

Bits

Bit Name

Description

Reset

Access

[31:0]

SCRATCH_DATA

Scratch Data.

0x0

R/W

MAC Reset Status Register

Address: 0x3B, Reset: 0x00000003, Name: MAC_RST_STATUS

If this register returns 0x00000000_00000001 when read, the oscillator clock is active, but the 25 MHz crystal clock is not active.

If this register returns 0x00000000_00000003 when read, both the oscillator clock and the 25 MHz crystal clock are active.

If this register returns 0x00000000_00000000 (SDO output pad is enabled while CS is low), the SPI follower and MAC core are both still in

reset.

Only single SPI reads of this register are supported. An SPI burst read must not increment into this register.

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