AT89C5132-ROTIL datasheet(116/181 Pages) ATMEL

116 / 181 page

116

4173D–USB–02/06

AT89C5132

18.6.3

Reset Address

On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast

addresses are XXXX XXXXb (all don’t-care bits). This ensures that the Serial Port is backwards

compatible with the 80C51 microcontrollers that do not support automatic address recognition.

18.7

Interrupt

The Serial I/O Port handles two interrupt sources that are the “end of reception” (RI in SCON)

and “end of transmission” (TI in SCON) flags. As shown in Figure 18-16 these flags are com-

bined together to appear as a single interrupt source for the C51 core. Flags must be cleared by

software when executing the serial interrupt service routine.

The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts are glo-

bally enabled by setting EA bit in IEN0 register.

Depending on the selected mode and whether the framing error detection is enabled or not, RI

flag is set during the stop bit or during the ninth bit as detailed in Figure 18-17.

Figure 18-16. Serial I/O Interrupt System

Figure 18-17. Interrupt Waveforms

18.8

Registers

Table 91. SCON Register

IEN0.4

Serial I/O

Interrupt Request

SCON.1

SCON.0

RXD

D1D2D3

D5D6

Start Bit

8-bit Data

Stop Bit

SMOD0 = X

SMOD0 = 1

a. Mode 1

b. Mode 2 and 3

RXD

D1D2D3

D5D6

Start bit

9-bit data

Stop bit

SMOD0 = 1

SMOD0 = 0

AT89C5132-ROTIL Folha de dados(PDF) 116 Page - ATMEL Corporation

AT89C5132-ROTIL Folha de dados(HTML) 116 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL