ADIN1100BCPZ-R7 datasheet(19/78 Pages) AD

19 / 78 page

Data Sheet

ADIN1100

THEORY OF OPERATION

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Rev. 0 | 19 of 78

Autonegotiation Fail

The autonegotiation can fail and can be caused by various scenar-

ios.

►

Configuration fault such as invalid master/slave configuration

►

Link quality issues

►

Timeout in pages transmission

If the autonegotiation fails, the link remains down until the autone-

gotiation process is restarted and completed.

MANAGEMENT INTERFACE

The MII management interface provides a 2-wire serial interface

between a host controller or external MAC chip and the ADIN1100

allowing access to control and status information in the subsystem

and PHY core management registers.

The MII management interface consists of the following:

►

MDC: clock line

►

MDIO: bidirectional data line

►

PHYAD_0, PHYAD_1, PHYAD_2: PHY address selection

►

INT: configurable management interrupt

The interface is compatible with both IEEE Standard 802.3 Clause

22 and Clause 45 management frame structures (see the Register

Summary section).

MDI Interface

The MDI connects the ADIN1100 to the Ethernet network via a

twisted wire pair.

The ADIN1100 requires an external hybrid circuit between the

TXN/TXP and RXN/RXP pins and the 10BASE-T1L twisted wire

pair. This function of the hybrid is to remove the local transmitted

signal from the combined signal on the cable, thereby allowing full

duplex operation on the 10BASE-T1L twisted wire pair.

An example circuit with the recommended topology and compo-

nents values is shown in Figure 13. Consider the size, power, and

voltage rating of these components in the context of other system

requirements, for example, requirements for intrinsic safety.

Figure 13. Recommended Hybrid for the ADIN1100

Hardware Interrupt (INT)

The ADIN1100 can generate a hardware interrupt to a host control-

ler or external MAC chip using the INT pin.

PHY Status Interrupts

The following conditions can be selected to generate an interrupt:

►

MAC interface frame checker/generator interrupt

►

MAC interface buffers overflow/underflow interrupt

►

Autonegotiation status change interrupt

►

Link status change interrupt

Those conditions can be set to enable an interrupt on the INT

pin using PHY_SUBSYS_IRQ_MASK (see the PHY Subsystem

Interrupt Mask Register section).

Following a hardware interrupt on the INT pin, the interrupt source

can be checked using PHY_SUBSYS_IRQ_STATUS (see the PHY

Subsystem Interrupt Status Register section).

Hardware Reset Interrupt

The ADIN1100 can also be configured to generate a hardware in-

terrupt after a hardware reset (RESET pin pulled low) by setting the

enable hardware reset interrupt bit (CRSM_HRD_RST_IRQ_EN)

in CRSM_IRQ_MASK (see the System Interrupt Mask Register

section).

Following a hardware interrupt on the INT pin, the interrupt

source can be checked with the CRSM_HRD_RST_IRQ_LH bit

in CRSM_IRQ_STATUS (see the System Interrupt Status Register

section).

Software Requested Interrupt

For system validation with an external host controller, the ADIN1100

can be requested to generate a hardware interrupt on the INT pin

using the CRSM_SW_IRQ_REQ bit in CRSM_IRQ_MASK (see the

System Interrupt Mask Register section).

Following a hardware interrupt on the INT pin, the interrupt

source can be checked with the CRSM_SW_IRQ_LH bit in

CRSM_IRQ_STATUS (see the System Interrupt Status Register

section).

System Error Interrupts

The ADIN1100 can also generate system errors interrupts. The

interrupt flags are located within the reserved bit sections of

CRSM_IRQ_STATUS (see the System Interrupt Status Register

section).

CRSM_IRQ_MASK (see the System Interrupt Mask Register sec-

tion) must be configured to allow system error interrupts. Refer

to Table 90 for details on the interrupts mask. The ADIN1100

must be hardware reset to recover from a system error interrupt

(CRSM_IRQ_STATUS reserved bits read as 1).

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