ADIN1100BCPZ-R7 datasheet(48/78 Pages) AD

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Data Sheet

ADIN1100

ETHERNET CLAUSE 45 REGISTER DETAILS

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Rev. 0 | 48 of 78

Table 48. Bit Descriptions for PMA_PMD_EXT_ABILITY

Bits

Bit Name

Description

Reset

Access

PMA_PMD_BT1_ABLE

PHY Supports BASE-T1. Indicates that the PHY supports BASE-T1 extended abilities as listed in

PMA_PMD_BT1_ABILITY.

0x1

[10:0]

RESERVED

Reserved.

0x0

BASE-T1 PMA/PMD EXTENDED ABILITY REGISTER

Device Address: 0x01; Register Address: 0x0012, Reset: 0x0004, Name: PMA_PMD_BT1_ABILITY

This address corresponds to the BASE-T1 PMA/PMD extended ability register specified in Clause 45.2.1.16 of Standard 802.3. This register is

read only, and writes have no effect.

Table 49. Bit Descriptions for PMA_PMD_BT1_ABILITY

Bits

Bit Name

Description

Reset

Access

[15:4]

RESERVED

Reserved.

0x0

B10S_ABILITY

10BASE-T1S Ability. This bit always reads as 0 because the PMA/PMD does not support 10BASE-T1S.

0x0

B10L_ABILITY

10BASE-T1L Ability. This bit always reads as 1 because the PMA/PMD supports 10BASE-T1L.

0x1

B1000_ABILITY

1000BASE-T1 Ability. This bit always reads as 0 because the PMA/PMD does not support 1000BASE-T1.

0x0

B100_ABILITY

100BASE-T1 Ability. This bit always reads as 0 because the PMA/PMD does not support 100BASE-T1.

0x0

BASE-T1 PMA/PMD CONTROL REGISTER

Device Address: 0x01; Register Address: 0x0834, Reset: 0x8002, Name: PMA_PMD_BT1_CONTROL

This address corresponds to the BASE-T1 PMA/PMD control register specified in Clause 45.2.1.185 of Standard 802.3.

Table 50. Bit Descriptions for PMA_PMD_BT1_CONTROL

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved.

0x1

CFG_MST

Master and Slave Configuration. CFG_MST is used only when autonegotiation is disabled. Otherwise,

this value is determined by the autonegotiation process itself. When this bit is set as 1, the device is

configured as a master. Otherwise, the device is configured as a slave.

Pin dependent

R/W

[13:4]

RESERVED

Reserved.

0x0

[3:0]

BT1_TYPE_SEL

BASE-T1 Type Selection. See IEEE Standard 802.3 for the following control register bit definitions (where

X means don't care):

0x2

R/W

1XXX: reserved.

01XX: reserved.

0011: 10BASE-T1S .

0010: 10BASE-T1L.

0001: 1000BASE-T.

0000: 100BASE-T.

BT1_TYPE_SEL is used only when autonegotiation is disabled and forced link configuration mode is

enabled. If autonegotiation is enabled, the PHY type is determined by the autonegotiation process itself.

Note that for ADIN1100, the only valid value is for 10BASE-T1L.

0010: 10BASE-T1L.

10BASE-T1L PMA CONTROL REGISTER

Device Address: 0x01; Register Address: 0x08F6, Reset: 0x0000, Name: B10L_PMA_CNTRL

This address corresponds to the 10BASE-T1L PMA control register specified in Clause 45.2.1.186a of Standard 802.3cg.

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