ADIN1100BCPZ-R7 datasheet(75/78 Pages) AD

75 / 78 page

Data Sheet

ADIN1100

ETHERNET CLAUSE 45 REGISTER DETAILS

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Rev. 0 | 75 of 78

FRAME GENERATOR DONE REGISTER

Device Address: 0x1F; Register Address: 0x8029, Reset: 0x0000, Name: FG_DONE

This register is used to indicate that the frame generator has completed the generation of the number of frames requested in the FG_NFRM_H

and FG_NFRM_L registers.

Table 136. Bit Descriptions for FG_DONE

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FG_DONE

Frame Generator Done. This bit reads as 1 to indicate that the generation of frames has completed. When set, this bit

goes high and it latches high until it is unlatched by reading.

0x0

R LH

RMII CONFIGURATION REGISTER

Device Address: 0x1F; Register Address: 0x8050, Reset: 0x0006, Name: RMII_CFG

Table 137. Bit Descriptions for RMII_CFG

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x3

RMII_TXD_CHK_EN

RMII TXD Check Enable. This bit determines whether or not TXD_1 to TXD_0 are monitored to detect the

start of a frame. It allows the RMII receiver CRS_DV signal to be connected to the RMII TX_EN signal. It is

mainly intended for debug and test purposes.

0x0

R/W

MAC INTERFACE LOOPBACKS CONFIGURATION REGISTER

Device Address: 0x1F; Register Address: 0x8055, Reset: 0x000A, Name: MAC_IF_LOOPBACK

MAC interface loopbacks configuration.

Table 138. Bit Descriptions for MAC_IF_LOOPBACK

Bits

Bit Name

Description

Reset

Access

[15:4]

RESERVED

Reserved.

0x0

MAC_IF_REM_LB_RX_SUP_EN

Suppress RX Enable. Suppress receiver to the MAC when MAC_IF_REM_LB_EN is set.

0x1

R/W

MAC_IF_REM_LB_EN

MAC Interface Remote Loopback Enable. Receive data is looped back to the transmitter.

0x0

R/W

MAC_IF_LB_TX_SUP_EN

Suppress Transmission Enable. Suppress transmission to the PHY when MAC_IF_LB_EN is

set.

0x1

R/W

MAC_IF_LB_EN

MAC Interface Loopback Enable. Transmit data is looped back to the receiver.

0x0

R/W

MAC START OF PACKET (SOP) GENERATION CONTROL REGISTER

Device Address: 0x1F; Register Address: 0x805A, Reset: 0x001B, Name: MAC_IF_SOP_CNTRL

Table 139. Bit Descriptions for MAC_IF_SOP_CNTRL

Bits

Bit Name

Description

Reset

Access

[15:6]

RESERVED

Reserved.

0x0

MAC_IF_TX_SOP_LEN_CHK_EN

Enable TX SOP Preamble Length Check.

0x0

R/W

MAC_IF_TX_SOP_SFD_EN

Enable TX SOP Signal Indication on start of frame delimiter (SFD).

0x1

R/W

MAC_IF_TX_SOP_DET_EN

Enable the Generation of the TX SOP Indication Signal.

0x1

R/W

MAC_IF_RX_SOP_LEN_CHK_EN

Enable RX SOP Preamble Length Check. If this bit is set and no SFD is received, the RX

SOP signal indication is set after eight bytes. Otherwise, the RX SOP is not set if no SFD is

received in the first eight bytes.

0x0

R/W

MAC_IF_RX_SOP_SFD_EN

Enable RX SOP Signal Indication on SFD Reception. If both MAC_IF_RX_SOP_DET_EN

and MAC_IF_RX_SOP_SFD_EN are set, the RX SOP signal is set when the SFD is

0x1

R/W

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