ADIN1100BCPZ-R7 datasheet(39/78 Pages) AD

39 / 78 page

Data Sheet

ADIN1100

ETHERNET CLAUSE 22 REGISTER DETAILS

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Rev. 0 | 39 of 78

Table 33. ADIN1100 Register Summary

Address

Name

Description

Reset

Access

0x0

MI_CONTROL

MII Control Register.

0x1100

R/W

0x1

MI_STATUS

MII Status Register.

0x1009

0x2

MI_PHY_ID1

PHY Identifier 1 Register.

0x0283

0x3

MI_PHY_ID2

PHY Identifier 2 Register.

0xBC81

0xD

MMD_ACCESS_CNTRL

MMD Access Control.

0x0000

R/W

0xE

MMD_ACCESS

MMD Access.

0x0000

R/W

MII CONTROL REGISTER

Address: 0x0, Reset: 0x1100, Name: MI_CONTROL

This address corresponds to the MII control register specified in Clause 22.2.4.1 of Standard 802.3.

Table 34. Bit Descriptions for MI_CONTROL

Bits

Bit Name

Description

Reset

Access

MI_SFT_RST

Software Reset. The software reset bit allows a software reset cycle to be initiated. Mirrors

CRSM_SFT_RST.

0x0

R/W SC

MI_LOOPBACK

Local Loopback (PCS). The loopback bit allows the PHY loopback mode to be engaged. Mirrors

LB_PCS_EN.

0x0

R/W

MI_SPEED_SEL_LSB

MII Speed Selection LSB. See MI_SPEED_SEL_MSB.

0x0

MI_AN_EN

Autonegotiation Enable. Use the AN_FRC_MODE_EN bit to enable forced link configuration mode.

Mirrors AN_EN.

0x1

0: disable autonegotiation.

1: enable autonegotiation.

MI_SFT_PD

Software Power-Down. The software power-down bit allows the PHY to be placed in software

power-down mode. In this mode, most of the PHY circuitry is switched off. However, MDIO access

to all registers is still possible. The default value for this register is configurable via the RX_DV/

RX_CTL/SWPD_EN pin, which allows the PHY to be held in reset until an appropriate software

initialization has been performed. Mirrors CRSM_SFT_PD.

Pin dependent

R/W

MI_ISOLATE

MII Isolate. The isolate bit allows the PHY to be isolated from the MII.

0x0

R/W

RESERVED

Reserved.

0x0

R/W SC

MI_FULL_DUPLEX

MII Full Duplex. The duplex mode bit cannot be written and always reads as 1 because the PHY is

only able to operate in full duplex mode.

0x1

MI_COLTEST

MII Collision Test. The collision test bit cannot be written and always reads as 0 because the PHY is

only able to operate in full duplex mode, and does not have a collision detect MII (COL) pin.

0x0

MI_SPEED_SEL_MSB

MII Speed Selection MSB. The speed selection MSB and LSB bits cannot be written and always

reads as 00 because the PHY is only able to operate at 10 Mbps.

0x0

MI_UNIDIR_EN

MII Unidirectional Enable. The unidirectional enable bit cannot be written and always reads as 0

because the PHY does not have the ability to transmit data from the MII regardless of whether it

has determined that a valid link has been established.

0x0

[4:0]

RESERVED

Reserved.

0x0

MII STATUS REGISTER

Address: 0x1, Reset: 0x1009, Name: MI_STATUS

This address corresponds to the MII status register specified in Clause 22.2.4.2 of Standard 802.3.

Table 35. Bit Descriptions for MI_STATUS

Bits

Bit Name

Description

Reset

Access

MI_T4_SPRT

100BASE-T4 Ability. The 100BASE-T4 ability bit always reads as 0 to indicate that the PHY does

not support this technology.

0x0

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