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Os motores de busca de Datasheet de Componentes eletrônicos |
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AD6688 Folha de dados(PDF) 113 Page - Analog Devices |
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AD6688 Folha de dados(HTML) 113 Page - Analog Devices |
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113 / 138 page  Data Sheet AD6688 Rev. 0 | Page 113 of 138 Addr. Name Bit(s) Bit Name Setting Description Reset Access 0x03C0 DDC3 Phase Increment Frac A0 [7:0] DDC3 Phase Increment Frac A[7:0] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x03C1 DDC3 Phase Increment Frac A1 [7:0] DDC3 Phase Increment Frac A[15:8] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x03C2 DDC3 Phase Increment Frac A2 [7:0] DDC3 Phase Increment Frac A[23:16] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x03C3 DDC3 Phase Increment Frac A3 [7:0] DDC3 Phase Increment Frac A[31:24] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x03C4 DDC3 Phase Increment Frac A4 [7:0] DDC3 Phase Increment Frac A[39:32] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x03C5 DDC3 Phase Increment Frac A5 [7:0] DDC3 Phase Increment Frac A[47:40] Numerator correction term for Modulus Phase Accumulator A. 0x0 R/W 0x03C8 DDC3 Phase Increment Frac B0 [7:0] DDC3 Phase Increment Frac B[7:0] Denominator correction term for Modulus Phase Accumulator B. 0x0 R/W 0x03C9 DDC3 Phase Increment Frac B1 [7:0] DDC3 Phase Increment Frac B[15:8] Denominator correction term for Modulus Phase Accumulator B. 0x0 R/W 0x03CA DDC3 Phase Increment Frac B2 [7:0] DDC3 Phase Increment Frac B[23:16] Denominator correction term for Modulus Phase Accumulator B. 0x0 R/W 0x03CB DDC3 Phase Increment Frac B3 [7:0] DDC3 Phase Increment Frac B[31:24] Denominator correction term for Modulus Phase Accumulator B. 0x0 R/W 0x03CC DDC3 Phase Increment Frac B4 [7:0] DDC3 Phase Increment Frac B[39:32] Denominator correction term for Modulus Phase Accumulator B. 0x0 R/W 0x03CD DDC3 Phase Increment Frac B5 [7:0] DDC3 Phase Increment Frac B[47:40] Denominator correction term for Modulus Phase Accumulator B. 0x0 R/W Digital Outputs and Test Modes Table 51. Addr. Name Bit(s) Bit Name Setting Description Reset Access 0x0550 ADC test mode control (local) 7 User pattern selection Test mode user pattern selection. This bit is only used when Register 0x0550, Bits[3:0] = 4’b1000 (user input mode). Otherwise, it is ignored. User Pattern 1 is found in the USR_PAT_1_MSB (0x0552) and USR_PAT_1_LSB (0x0551) registers. User Pattern 2 is found in the USR_PAT_2_MSB (0x0554) and USR_PAT_2_LSB (0x0553) registers, and so on. 0x0 R/W 0 Continuous/repeat pattern. Place each user pattern (1, 2, 3, and 4) on the output for 1 clock cycle and then repeat. (Output User Pattern 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, and so on.) 1 Single pattern. Place each user pattern (1, 2, 3, and 4) on the output for 1 clock cycle and then output all zeros. (Output User Pattern 1, 2, 3, 4, and then output all zeros.) 6 Reserved Reserved. 0x0 R 5 Reset PN long generator Test mode long pseudorandom number test generator reset. 0x0 R/W 0 Long PN enabled. 1 Long PN held in reset. 4 Reset PN short generator Test mode short pseudorandom number test generator reset. 0x0 R/W 0 Short PN enabled. 1 Short PN held in reset. |
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