AM652X datasheet(260/299 Pages) TI1

260 / 299 page

260

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

•

Display Controller (DISPC), with the following main features

–

One Direct Memory Access (DMA) engine

–

One Video Pipeline (VID1), including VC1 Range Mapping Unit, Scaler, and Color Space Converter

(CSC)

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One Overlay Manager (OVR1)

–

Active Matrix color support for 12/16/18/24-bit (truncated or dithered encoded pixel values)

–

One Video Port (VP1) with programmable timing generator to support up to 148.5 MHz pixel clock

video formats defined in CEA-861-E and VESA DMT standards

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Supported maximum FrameBuffer width of 4096 for all pixel formats

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Configurable output mode: progressive or interlaced

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Selection between RGB and YUV422 output pixel formats (YUV422 only available when BT-656 or

BT-1120 output mode is enabled on the parallel interface)

–

Stall Mode support for RFBI

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Remote Frame Buffer Interface (RFBI) module, with the following main features:

–

Access to RFB direct “Arm interface”

•

Sending commands and data to the RFB panel, received from DISPC or from Arm (through the

32-bit interconnect slave port)

•

Reading data/status from the RFB through the 32-bit interconnect slave port

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RFB interface:

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8/9/12/16-bit data bus (for up to QVGA @30fps)

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Two programmable configurations for two peripheral devices connected to the RFBI module

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Tearing Effect control logic: Horizontal Synchronization (HSync) and Vertical Synchronization

(VSync) embedded in a single signal (TE) or using two signals (HS+VS)

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Programmable pixel memory and output formats

DSS provides two interfaces to SoC interconnect:

•

One 128-bit master port (with MFLAG support). The DMA engine in DISPC uses this single master port

to read data from SoC system memory.

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One 32-bit slave port. Used for configuration of the memory mapped registers inside DSS. It is further

connected internally to DISPC and RFBI modules.

Display outputs can connect seamlessly to an OpenLDI interface or can drive device pins as a parallel

video output interface. The OLDI_TX module is an Open LVDS Display Interface transmitter is designed to

support serialized RGB pixel data transmission between a host and flat panel display over LVDS signal

lines. It translates 21 or 28 bit wide video and sync data into 3 or 4 bit wide serial data 7 bits deep.

The OLDI_TX module include the following features:

•

OLDI Mapping

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3 or 4 LVDS data channels

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VESA or JEIDA bit mapping

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Multiple OLDI Link Modes

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Single Link (Duplicate or non-duplicate mode)

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Dual Link (master or slave mode)

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Link Disable

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Clock Transmission

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ANSI/TIA/EIA644-A compliant VLVDS signaling

OLDI_TX Not Support features:

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DC balanced mode on LVDS output

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Hot plug detection

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EDID/DDC

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