AM652X datasheet(259/299 Pages) TI1

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259

AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

•

DDR PHY Features:

–

Partial data macro use for ECC in 39-bit and 22-bit mode

–

Automatic and software controllable DDR-PHY and I/Os initialization and calibration (ZQ)

–

Automatic and software controllable delay line calibrations with voltage and temeprature (VT)

compensation

–

Automatic and software controllable write levelling with VT compensation

–

Automatic read DQS gating training per rank with VT compensation

–

Automatic and software controllable DQ/DQS eye training per rank

–

Automatic and software controllable read and write data bit deskew

–

Automatic and software controllable Command/Address (CA) levelling with VT compensation for

LPDDR4

–

Automatic and software controllable CA bit deskew for LPDDR4

–

Refreshes to SDRAM during leveling and training

–

Any bit in the byte lane as prime bit for write leveling and read trainings

–

No seeding requirement based on board topology for any of the leveling and training algorithms

–

Max channel length of 3 inches with controlled impedance for command and data channels

–

Dynamic/automatic I/O receiver disable when read transfer is not on going

–

Capability of disabling unused data macros and I/Os when not in use

–

Ability to keep DLL/PLL ON during stress/burn-in testing (BIST loopback with DLL/PLL operational

but not used)

DDRSS0 does not support the following:

•

4-bit wide DDR4 devices

•

UDIMMs

•

SODIMMs

•

RDIMMs

•

LRDIMMs

•

Address mirroring for DIMMs

•

Data bus obfuscation or any other kind of encryption

•

Automatic periodic scrubbing of SDRAM for ECC

–

Does not support the ECC Scrubber block provided by Synopsys for a fully automated flexible

scrubbing solution

•

32-bit with ECC (39-bit) for LPDDR4

•

8-bit with ECC (13-bit) for LPDDR4

•

8-bit without ECC for LPDDR4

•

Two independent 16-bit channel operation for LPDDR4

For more information, see section DDR Subsystem (DDRSS) in chapter Peripherals of the device TRM.

6.11.6 DSS

The Display Subsystem (DSS) provides the logic to interface display peripherals. DSS includes a DMA

engine as part of the integrated Display Controller (DISPC) module, which allows direct access to the

frame buffer (system memory). Various pixel processing capabilities are supported, such as: color space

conversion, filtering, scaling, among others.

The supported display interfaces (connections to external panel) are:

•

One parallel interface, which can be used for MIPI® DPI 2.0, or BT-656 or BT-1120.

•

One RFBI interface, supporting MIPI DBI 2.0.

The modules integrated in DSS are:

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