AM652X datasheet(258/299 Pages) TI1

258 / 299 page

258

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

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Key Features:

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Full coherency across all commands

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Bank interleaving

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Priority based scheduling

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Scheduling based on bank openness

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Class of Service (CoS)

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Three latency classes supported

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Programmable counters to tune CoS

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Read/write scheduling to avoid turn-around time

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Prioritized refresh scheduling

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Dynamic change of refresh rate via software for extended temperatures

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Statistical counters for performance management

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ECC Features:

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SECDED for 32-bit interface (39-bit with ECC)

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Supported only for DDR4

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SECDED for 16-bit interface (22-bit with ECC)

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Supported for DDR4 and LPDDR4

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SECDED for 8-bit interface (13-bit with ECC)

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Supported only for DDR4

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Read-modify-write ECC for sub-word writes

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ECC address error logging

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Statistical counters for counting ECC errors

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Injecting ECC errors during normal operation for validation

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Automatic ECC scrub operation inside the Synopsys DDR Controller for any read command

received which has led to a single-bit error.

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At any time, only one outstanding ECC scrub operation is allowed inside the Synopsys DDR

Controller

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Low Power Features:

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All power modes defined by JEDEC (clock stop for LPDDRx, self-refresh, power-down, etc.)

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Self-refresh entry and exit via software or clock stop req/ack

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System bus clock stop via clock stop request when controller is idle

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Automatic idle power saving mode when no or low activity is detected

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DDR and system bus clock frequency change using self-refresh via software or clock stop request

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Turning off SoC power after DDR is put into self-refresh (DDR reset and CKE IO retention)

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Functional Safety Features:

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ECC on data

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Parity on address and command

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ECC on internal RAMs

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