AM652X datasheet(257/299 Pages) TI1

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257

AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

6.11.4 DCC

The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time

execution of an application. Specifically, the DCC is expected to detect 2% drift from the expected

frequency within 100ms time. Moreover, the exact accuracy can also be programed based on calculation

for each application. In addition, the DCC can also measure the frequency of a selectable clock source

using another input clock as a reference.

The device has eleven instances of DCC modules.

The DCC uses two independent clock sources to detect when one is out of spec. Each DCC module

implements the following features:

•

Two independent counter blocks count clock pulses from each clock source

•

Each counter block is programmable, however, for proper operation the counters must be programmed

with seed values that respect the ratio of the two clock frequencies

•

Configurable timebase for error signal

•

Error signal generation when one of the clocks is out of spec

•

Clock frequency measurement

For more information, see section Dual Clock Comparator (DCC) in chapter Peripherals of the device

TRM.

6.11.5 DDR Subsystem (DDRSS)

The DDR subsystem in this device comprises Synopsys DDR controller, Synopsys DDR PHY and wrapper

logic to integrate these Synopsys blocks in the device. The DDR subsystem is referred to as DDRSS0 and

is used to provide an interface to external SDRAM devices which can be utilized for storing program or

data. DDRSS0 is accessed via MSMC, and not directly through the system interconnect.

The DDRSS0 supports:

•

Memory Types:

–

DDR3L

–

DDR4

–

LPDDR4

•

Memory Bus Features:

–

39-bit width with ECC (32 bits for data and 7 bits for ECC)

–

1/2 width (22-bit) mode via software configuration

–

1/4 width (13-bit) mode via software configuration

–

Up to 1 rank

–

SDRAM address range up to 32 GB

•

System Bus Interface:

–

256-bit data width

–

Clock asynchronous to DDR clock

–

Little endian only

–

Address aliasing prevention to block accesses to unpopulated SDRAM region

•

Configuration Bus Interface:

–

32-bit data width

–

Linear incrementing addressing mode

–

32-bit aligned accesses only

–

Little endian only

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