AM652X datasheet(254/299 Pages) TI1

254 / 299 page

254

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

6.11 Peripherals

6.11.1 ADC

The analog-to-digital converter (ADC) module is an 8 channel general purpose analog-to-digital converter,

which supports 12-bit conversion samples from an analog front end (AFE).

There are total of two ADC modules in the device.

Each ADC module has the following features:

•

8 channels

•

12-bit data

•

4 MSPS at 60 MHz sample clock

•

Programmable Finite State Machine (FSM) sequencer that supports 15 steps:

–

Software register bit for start of conversion

–

Optional start-of-conversion (SOC) synchronized to external hardware event

–

Single conversion (one-shot)

–

Continuous conversions

–

Sequence through all input channels based on a mask

–

Programmable open delay before sampling each channel

–

Programmable sampling delay for each channel

–

Programmable averaging of input samples - 16, 8, 4, 2, or 1

–

Store data in either of two FIFO – 256-word 16-bit RAM

–

Option to encode channel number with data

–

Support for servicing FIFOs via DMA or CPU

–

Programmable DMA Request event (for each FIFO)

–

Dynamically enable or disable channel inputs during operation

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Stop bit to end conversion

–

Support for error offset (internal calibration or external calibration via eFuse) inside the AFE

•

Support for the following interrupts and status, with masking:

–

Interrupt after a sequence of conversions (all non-masked channels)

–

Interrupt for FIFO threshold levels

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Interrupt if sampled data is out of a programmable range

–

Interrupt for FIFO overflow and underflow conditions

–

Status bit to indicate if ADC is busy converting

ADC Not Supported Features:

•

No packing of 16-bit FIFO data onto 32-bit DMA bus

•

No support for big endian

•

Support only 32-bit aligned read/write accesses on the MCU_CBASS0/DMA ports

For more information, see section Analog-to-Digital Converter (ADC) in chapter Peripherals of the device

TRM.

6.11.2 CAL

The device has one Camera Adaptation Layer (CAL) controller with MIPI Camera Serial Interface 2 and

LVDSRX parallel bypass port.

The CAL supports the following modules and configurations:

•

The CSI-2 port support one 4-Lane D-PHY

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