AM652X datasheet(255/299 Pages) TI1

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255

AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

•

4-Lane D-PHY

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Based on MIPI DSI PHY specifications 1.2 with custom enhancements to support LVDS sensors

and ESD enhancements to support Q100. Support 1.5Gbps per lane.

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LVDSRX

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Support generic parallel I/F (H/VSYNC+DATA+CLOK) protocol. LVDSRX module implements

generic parallel interface and sends captured data to CAL module over proprietary BYS interface.

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Support non MIPI Serial LVDS interface

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Embedded sync decode

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4 complex I/O connections

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Support 8, 10, 12, 14 and 16 bits RAW mode

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Support BYS I/F with up to 4 pixels/ cycle, each pixel is 16bit wide

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Support Video I/F with 1 pixel / cycle or 2 pixel / cycle, each pixel is 16bit wide

CAL Not Supported Features:

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Integrated ISP

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ECC on CAL memories for functional safety

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Parallel LVDS sensors

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Hardware scalers

For more information, see section Camera Adaptation Layer (CAL) in chapter Peripherals of the device

TRM.

6.11.3 CPSW2G

The two-port Gigabit Ethernet switch subsystem (MCU_CPSW0) provides ethernet packet communication

for the device and can be configured as an ethernet switch. MCU_CPSW0 features the Reduced Gigabit

Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the

Management Data Input/Output (MDIO) interface for physical layer device (PHY) management.

The MCU_CPSW0 subsystem provides the following features:

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One Ethernet port (port 1) with selectable RGMII and RMII interfaces and an internal (CPPI) port (port

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Synchronous 10/100/1000 Mbit operation

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Flexible logical FIFO-based packet buffer structure

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Eight priority level Quality Of Service (QOS) support (802.1p)

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Support for Audio/Video Bridging (P802.1Qav/D6.0)

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Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)

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Timestamp module capable of time stamping external timesync events like Pulse-Per-Second and

also generating Pulse-Per-Second outputs

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CPTS module that supports time stamping for IEEE1588 with support for 4 hardware push events

and generation of compare output pulses

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DSCP Priority Mapping (IPv4 and IPv6)

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Energy Efficient Ethernet (EEE) support (802.3az)

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Priority Based Flow Control (802.1QBB) and Flow Control (802.3x) Support

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Non Blocking switch fabric

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Time Sensitive Network Support

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IEEE P902.3br/D2.0 Interspersing Express Traffic

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IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic

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