AM652X datasheet(253/299 Pages) TI1

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253

AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

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Provides 1 memory write access unit (Write Unit 0):

–

Supports write bursts up to 32 bytes (limited by Tx Per-Channel FIFO depth)

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Provides a 32-bit wide VBUSP write-only master interface for peripheral accesses

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Supports up to 8 outstanding writes

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Provides 1 memory read access unit (Read Unit 0):

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Supports 1 outstanding read per interface (VBUSP)

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Supports read burst up to 32 bytes (limited by Rx Per-Channel FIFO depth)

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Provides a 32-bit wide VBUSP read-only master interface for peripheral accesses

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Supports up to 23 simultaneous destination (Tx) channels

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Supports up to 23 simultaneous source (Rx) channels

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Supports static Transfer Requests (TRs) only

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Supports MCAN special transfer mode

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Provides per-channel buffering:

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Provides 8x128-bit word deep data FIFO for each destination channel

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Provides 8x128-bit word deep data FIFO for each source channel

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Provides 128-bit wide PSI-L compliant data interface to remote UDMA and remote peripherals

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Includes 1 output event transport lane

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Provides 128-bit wide PSI-L compliant data interface from remote UDMA and remote peripherals

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Includes 1 input event transport lane

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Includes support for converting 16 local events to global events with corresponding mapping registers

6.10.1.1.5 PDMA_DEBUG Features

The Debug PDMA supports the following features:

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Implements CPPI 5.0 compliant third-party Unified Transfer Controller (UTC)

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Provides 0 memory write access units

•

Provides 1 memory read access unit (Read Unit 0):

–

Supports 1 outstanding read per interface (VBUSP)

–

Supports read burst up to 32 bytes (limited by Rx Per-Channel FIFO depth)

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Provides a 64-bit wide VBUSP read-only master interface for peripheral accesses

•

Supports up to 0 simultaneous destination (Tx) channels

•

Supports up to 3 simultaneous source (Rx) channels

•

Supports static Transfer Requests (TRs) only

•

Supports MCAN special transfer mode

•

Provides per-channel buffering:

–

Provides 8x128-bit word deep data FIFO for each destination channel

–

Provides 8x128-bit word deep data FIFO for each source channel

–

Provides 128-bit wide PSI-L compliant data interface to remote UDMA and remote peripherals

–

Includes 1 output event transport lane

–

Provides 128-bit wide PSI-L compliant data interface from remote UDMA and remote peripherals

–

Includes 1 input event transport lane

6.10.1.2 PDMA Not Supported Features

The following unsupported features apply to all PDMA modules in the device:

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Dynamic Transfer Requests are not supported

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Cross Channel Triggering is not supported

For more information, see section PDMA Controller in chapter DMA Controllers of the device TRM.

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