AM652X datasheet(249/299 Pages) TI1

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249

AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

6.8

Memory Subsystem

6.8.1

MSMC

The

Multi-core

Shared

Memory

Controller

(MSMC)

forms

the

heart

the

compute

cluster

(COMPUTE_CLUSTER0) providing high-bandwidth resource access both to and from all of the connected

processing elements and the rest of the system. MSMC serves as the data-movement backbone of the

compute cluster.

MSMC supports the following features:

•

2MB (2 banks x 1MB) SRAM with ECC:

–

Shared coherent level 2/level 3 memory-mapped SRAM

–

Shared coherent level 3 cache

•

256-bit processor port bus and 40-bit physical address bus

•

Coherent unified bi-directional interfaces to connect to processors or device masters

•

One infrastructure master interface

•

Single external memory master interface

•

Supports distributed virtual system

•

Supports internal DMA engine – DRU (Data Routing Unit)

–

DMA in/out L2 SRAM, MSMC, DDR and system

–

L2, L3 cache pre-warming and post flushing

•

Bandwidth management with starvation bound

•

Two-level QoS support for real-time/non-real-time split

•

Security firewall for SRAM/cache and external memory

•

ECC error protection

•

Scrubbing on MSMC data memory (no scrubbing on tag RAMs or memory blocks used by DRU)

•

Parity protection and detection on all addresses, routing control and SECDED protection on data

pipelines

•

One interconnect messaging interface that supports DMA/prefetch requests to DRU

•

Trace and debugging support

•

Supports dynamic power up and power down on PDs low power modes, if required by system

applications

•

Supports dynamic clock gating on all logic units

•

Supports low power mode during low-usage processor states

MSMC does not support the following:

•

Cache coherence between multiple MSMC clusters

•

Atomic operation for compute cluster interface

•

AMBA-style exclusive bus operations to strongly ordered, device, or non-cacheable memory locations.

•

DRU memory management unit

•

PSI-L supported MMU control messaging

For more information, see section Multicore Shared Memory Controller (MSMC) in chapter Device

Configuration of the device TRM.

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