CS89712 datasheet(49/170 Pages) CIRRUS

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CS89712

DS502PP2

2.26.4.2

Runt Frame

If a frame is received that is shorter than 64 bytes,

the Runt bit (RxEvent register, Bit D) is set. If the

RuntA bit (RxCTL register, Bit D) is set, the frame

will still be buffered by Ethernet port. If the RuntiE

bit (RxCFG bit D) is set, an interrupt is generated.

2.26.4.3

Extra Data

If a frame is received that is longer than 1518 bytes,

the Extradata bit (RxEvent register, Bit E) is set. If

the ExtradataA bit (RxCTL register, Bit E) is set,

the first 1518 bytes of the frame will still be buff-

ered by Ethernet port. If the ExtradataiE bit (Rx-

CFG register Bit E) is set, an interrupt is generated.

2.26.4.4

Dribble Bits and Alignment Error

Under normal operating conditions, the MAC may

detect up to 7 additional bits after the last full byte

of a receive packet. These bits, known as dribble

bits, are ignored. If dribble bits are detected, the

Dribblebit bit (RxEvent register, Bit 7) is set. If

both the Dribblebits bit and CRCerror bit (RxEvent

ment error has occurred.

2.26.5

Media Access Management

The Ethernet network topology is a single shared

medium with several attached stations. The Ether-

net protocol is designed to allow each station equal

access to the network at any given time. Any node

can attempt to gain access to the network by first

completing a deferral process (described below) af-

ter the last network activity, and then transmitting a

packet that will be received by all other stations. If

two nodes transmit simultaneously, a collision oc-

curs and the colliding packets are corrupted. Two

primary tasks of the MAC are to avoid network col-

lisions, and then recover when they occur.

2.26.5.1

Collision Avoidance

The MAC continually monitors network traffic by

checking for the presence of carrier activity (carrier

activity is indicated by the assertion of the internal

Carrier Sense signal generated by the ENDEC). If

carrier activity is detected, the network is assumed

busy and the MAC must wait until the current

packet is finished before attempting transmission.

The Ethernet port supports two schemes for deter-

mining when to initiate transmission: Two-Part De-

ferral, and Simple Deferral. Selection of the

deferral scheme is determined by the 2-partDefDis

bit (LineCTL register bit D). If the 2-partDefDis bit

is clear, the MAC uses a two-part deferral process

defined in section 4.2.3.2.1 of the Ethernet standard

(ISO/IEC 8802-3, 1993). If the 2-partDefDis bit is

set, the MAC uses a simplified deferral scheme.

Both schemes are described below:

2.26.5.2

Two-Part Deferral

In the two-part deferral process, the 9.6 µs Inter

Packet Gap (IPG) timer is started whenever the in-

ternal Carrier Sense signal is deasserted. If activity

is detected during the first 6.4 µs of the IPG timer,

the timer is reset and then restarted once the activi-

ty has stopped. If there is no activity during the first

6.4 µs of the IPG timer, the IPG timer is allowed to

time out (even if network activity is detected during

the final 3.2 µs). The MAC then begins transmis-

sion if a transmit packet is ready and if it is not in

Backoff (Backoff is described later in this section).

If no transmit packet is pending, the MAC contin-

ues to monitor the network. If activity is detected

before a transmit frame is ready, the MAC defers to

the transmitting station and resumes monitoring the

network.

The two-part deferral scheme was developed to

prevent the possibility of the IPG being shortened

due to a temporary loss of carrier. Figure 14 dia-

grams the two-part deferral process.

2.26.5.3

Simple Deferral

In the simple deferral scheme, the IPG timer is

started whenever Carrier Sense is deasserted. Once

the IPG timer is finished (after 9.6 µs), if a transmit

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