CS89712 datasheet(83/170 Pages) CIRRUS

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CS89712

DS502PP2

3.5.2

SYSCON2 System Control Register 2 (address 0x8000.1100)

This is an extension of SYSCON1, containing additional control for the CS89712. The bits of this second system

control register are defined below. The SYSCON2 register is reset to all 0s on power up.

11:10

Reserved

BUZFREQ

CLKENSL

OSTB

Reserved

SS2MAEN

UART2EN

54321

SS2RXEN

PC CARD2

PC CARD1

SS2TXEN

KBWEN

DRAMSZ

KBD6

SERSEL

Bit

Description

SERSEL:The only affect of this bit is to select either SSI2 or the codec to interface to the external

pins. See the table below for the selection options.

NOTE: If the DAI bit of SYSCON3 is set, then it overrides the state of the SERSEL bit, and thus

the external pins are connected to the DAI interface.

KBD6: The state of this bit determines how many of the Port A inputs are OR’ed together to cre-

ate the keyboard interrupt. When zero (the reset state), all eight of the Port A inputs will generate

a keyboard interrupt. When set high, only Port A bits 0 to 5 will generate an interrupt from the

keyboard. It is assumed that the keyboard row lines are connected into Port A.

DRAMZ: This bit determines the width of the DRAM memory interface, where: 0=32-bit DRAM

and 1=16-bit DRAM.

KBWEN: When the KBWEN bit is high, the CS89712 will awaken from a power saving state into

the Operating State when a high signal is on one of Port A’s inputs (irrespective of the state of the

interrupt mask register). This is called the Keyboard Direct Wakeup mode. In this mode, the inter-

rupt request does not have to get serviced. If the interrupt is masked (i.e., the interrupt mask reg-

ister 2 (INTMR2) bit 0 is low), the processor simply starts re-executing code from where it left off

before it entered the power saving state. If the interrupt is non-masked, then the processor will

service the interrupt.

SS2TXEN: Transmit enable for the synchronous serial interface 2. The transmit side of SSI2 will

be disabled until this bit is set. When set low, this bit also disables the SSICLK pin (to save

power) in master mode, if the receive side is low.

PC CARD1: Enable for the interface to the CL-PS6700 device for PC Card slot 1. The main effect

of this bit is to reassign the functionality of Port B, bit 0 to the PRDY input from the CL-PS6700

devices, and to ensure that any access to the nCS4 address space will be according to the

CL-PS6700 interface protocol.

PC CARD2: Enable for the interface to the CL-PS6700 device for PC Card slot 2. The main effect

of this bit is to reassign the functionality of Port B, bit 1 to the PRDY input from the CL-PS6700

devices and to ensure that any access to the nCS5 address space will be according to the

CL-PS6700 interface protocol.

Table 38. SYSCON2

SERSEL Value

Selected Serial Device to

External Pins

Master / slave SSI2

Codec

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