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UCD3138ARMHT Folha de dados(PDF) 58 Page - Texas Instruments |
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UCD3138ARMHT Folha de dados(HTML) 58 Page - Texas Instruments |
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58 / 87 page  58 UCD3138A SLUSC66C – MARCH 2015 – REVISED SEPTEMBER 2016 www.ti.com Submit Documentation Feedback Product Folder Links: UCD3138A Application and Implementation Copyright © 2015–2016, Texas Instruments Incorporated 8.3.1 Design Requirements Table 8-2. Input Characteristics PARAMETER CONDITIONS MIN TYP MAX UNIT ALL SPECIFICATIONS at Vin = 400V and 25°C AMBIENT UNLESS OTHERWISE NOTED. Vin Input voltage range Normal Operating 350 385 420 V Vinmax Max input voltage Continuous 420 V Iin Input current Vin = 350V, Full Load 1.15 A Istby Input no load current Output current is 0A 30 mA Von Undervoltage lockout Vin Decreasing (input voltage is detected on secondary side) 340 V Vhys Vin Increasing 360 V (1) Ripple and noise are measured with 10-µF Tantalum capacitor and 0.1-µF ceramic capacitor across output. Table 8-3. Output Characteristics PARAMETER CONDITIONS MIN TYP MAX UNIT ALL SPECIFICATIONS at Vin = 400V and 25°C AMBIENT UNLESS OTHERWISE NOTED. VO Output voltage setpoint No load on outputs 12 V Regline Line regulation All outputs; 360 ≤ Vin ≤ 420; IO = IOmax 0.5% Regload Load regulation All outputs; 0 ≤ IO ≤ IOmax; Vin = 400 V 1% Vn Ripple and noise(1) 5 Hz to 20 MHz 100 mVpp IO Output current 0 30 A η Efficiency at phase-shift mode Vo = 12 V, Io = 15 A 93% η Efficiency at PWM ZVS mode Vo = 12 V, Io = 15 A 93% η Efficiency at hard switching mode Vo = 12 V, Io = 15 A 90% Vadj Output adjust range 11.4 12.6 V Vtr Transient response overshoot/undershoot 50% load step at 1 AµS, min load at 2 A ±0.36 V tsettling Transient response settling time 100 µS tstart Output rise time 10% to 90% of Vout 50 mS Overshoot At startup 2% fs Switching frequency Over Vin and IO ranges 150 kHz Ishare Current sharing accuracy 50% - Full load ±5% φ Loop phase margin 10% - Full load 45 ° G Loop gain margin 10% - Full load 10 dB 8.3.2 Detailed Design Procedure 8.3.2.1 PCMC (Peak Current Mode Control) PSFB (Phase-Shifted Full Bridge) Hardware Configuration Overview The hardware configuration of the UCD3138A PCMC PSFB converter contains two critical elements that are highlighted in the Section 8.3.2.2 and Section 5.7.1.8 sections. 8.3.2.2 DPWM Initialization for PSFB This section describes the key register settings and considerations necessary for the UCD3138A to generate the correct MOSFET waveforms for this topology. This maintains the proper phase relationship between the MOSFETs and synchronous rectifiers as well as the proper set up required to function correctly with PCMC. The UCD3138A DPWM peripheral provides flexibility for a wide range of topologies. The PSFB configuration utilizes the Intra-Mux and Edge Generation Modules of the DPWM. For a diagram showing these modules, see the UCD3138A Digital Power Peripherals Manual. |
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