UCD3138ARMHT datasheet(18/87 Pages) TI1

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UCD3138A

SLUSC66C – MARCH 2015 – REVISED SEPTEMBER 2016

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Specifications

(1)

Fast mode, 400 kHz

(2)

The device times out when any clock low exceeds t(TIMEOUT).

(3)

t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This

specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).

(4)

t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

(5)

Cb (pF)

5.6

PMBus/SMBus/I

2C Timing

The timing characteristics and timing diagram for the communications interface that supports I

2C, SMBus, and PMBus in

Slave or Master mode are shown in Section 5.6, Figure 5-1, and Figure 5-2. The values in Section 5.6 describe device

functional during 400 kHz operating frequency. However, the device supports all three speeds, standard (100 kHz), fast (400

kHz).

Typical values at TA = 25°C and VCC = 3.3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fSMB

SMBus/PMBus operating frequency

Slave mode, SMBC 50% duty cycle

100

400

kHz

fI2C

I2C operating frequency

Slave mode, SCL 50% duty cycle

100

400

kHz

t(BUF)

Bus free time between start and stop(1)

1.3

µs

t(HD:STA)

Hold time after (repeated) start(1)

0.6

µs

t(SU:STA)

Repeated start setup time(1)

0.6

µs

t(SU:STO)

Stop setup time(1)

0.6

µs

t(HD:DAT)

Data hold time

Receive mode

t(SU:DAT)

Data setup time

100

t(TIMEOUT)

Error signal/detect(2)

t(LOW)

Clock low period

1.3

µs

t(HIGH)

Clock high period(3)

0.6

µs

t(LOW:SEXT)

Cumulative clock low slave extend time(4)

Clock/data fall time

Rise time tr = (VILmax – 0.15) to (VIHmin

+ 0.15)

20 + 0.1

Cb(5)

300

Clock/data rise time

Fall time tf = 0.9 VDD to (VILmax –

0.15)

20 + 0.1

Cb(5)

300

Total capacitance of one bus line

400

Figure 5-1. I2C/SMBus/PMBus Timing Diagram

Figure 5-2. Bus Timing in Extended Mode

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