AD7993 datasheet(25/27 Pages) AD

25 / 27 page

AD7994/AD7993

–25–

REV. PrF

PRELIMINARYTECHNICAL DATA

Mode 2 -

This mode allows a conversion to be automatically initi-

ated anytime a read operation occurs. In order to use this

mode the command bits C4 - C1 in the Address Pointer

Byte shown in Table II must be programmed.

To select a particular Analog input for conversion in this

mode, then the user must set the corresponding channel

command bit to 1 in the Address Pointer Byte, see Table

XIII. When all four command bits are 0 then this mode is

not in use. A sequence can also be set up for this mode, if

more than one of the command bit in the Address Pointer

Byte are set. The ADC will start converting on the lowest

channel in the sequence and then the next lowest until all

the channels in the sequence have been converted on.

Figure 13 illustrates a two byte read operation from the

Conversion Result Register. This operation would nor-

mally be preceded by a write to the Address Pointer Regis-

ter so that the following read will access the desired

ure 10. When the contents of the Address Pointer Register

are being loaded, if the command bits C4 to C1 are set

then the AD7994/AD7993 will begin to power up and

convert upon the selected channel(s), power-up will begin

on the fifth SCL falling edge of the Address Point Byte,

see point A Figure 17. Table XIII shows the channel se-

lection in this mode via the command bits, C4 to C1 in

the Address Pointer Register. The wake-up and conversion

time together should take approximately 3

µs. Following

this, the AD7994/AD7993 must be addressed again to tell

it that a read operation is required.

The read then takes

place from the Conversion Result register. This read will

access the result from the conversion selected via the com-

mand bits. If the Command bits C2, C1 were set to 1,1,

then a four byte read would be necessary. The first read

accesses the data from the conversion on VIN1. While this

read takes place, a conversion occurs on VIN2. The second

read will access this data from VIN2. Figure 18 illustrates

how this mode operates.

When operating the AD7994-1/AD7993-1 in Mode2 with

Hs-Mode, 3.4 MHz SCL, the conversion may not be

complete before the master tries to read the conversion

result, if this is the case the AD7994-1/AD7993-1 will

hold the SCL line low after the read address during the

ACK clock, until the conversion is complete. When the

conversion is complete the AD7994-1/AD7993-1 will

release the SCL line and the master can then read the

conversion result.

Table XIII Address Pointer Byte

Analog Input Channel

Mode 2 not selected

Mode 2 Convert on VIN1

Mode 2 Convert on VIN2

Mode 2 Sequence between VIN1 and VIN2

Mode 2 Convert on VIN3

Mode 2 Sequence between VIN1 and VIN3

Mode 2 Sequence between VIN2 and VIN3

Mode 2 Sequence between VIN1, VIN2 and VIN3

Mode 2 Convert on VIN4

Mode 2 Sequence between VIN1 and VIN4

Mode 2 Sequence between VIN2 and VIN4

Mode 2 Sequence between VIN1, VIN2 and VIN4

Mode 2 Sequence between VIN3 and VIN4

Mode 2 Sequence between VIN1, VIN3 and VIN4

Mode 2 Sequence between VIN2, VIN3 and VIN4

Mode 2 Sequence between VIN1, VIN2, VIN3 and VIN4

With the pointer bits set to all 0’s then the next read will

access the results of the conversion Result Register.

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