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AD7993 Folha de dados(PDF) 6 Page - Analog Devices

Nome de Peças AD7993
Descrição Electrónicos  4-Channel, 12-/10-Bit ADCs with I2C Compatible Interface in 16-Lead TSSOP
PDF  27 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

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AD7994/AD7993
–6–
REV. PrF
PRELIMINARYTECHNICAL DATA
AD7994/AD7993
Limit at TMIN, TMAX
Parameter
Conditions
MIN
MAX
Unit
Description
t4
Standard Mode
0
3.45
µst
HD;DAT, Data Hold Time
Fast Mode
0
0.9
µs
High-Speed Mode, CB = 100pF max 0
70
ns
High-Speed Mode, CB = 400pF max 0
150
ns
t5
Standard Mode
4.7
µst
SU;STA, Set-up Time for a repeated START
Fast Mode
0.6
µs
Condition
High-Speed Mode
160
ns
t6
Standard Mode
4
µst
HD;STA, Hold Time (repeated) START
Fast Mode
0.6
µs
Condition
High-Speed Mode
160
ns
t7
Standard Mode
4.7
µst
BUF, Bus Free Time Between a STOP and a
Fast Mode
1.3
µs
START Condition.
t8
Standard Mode
4
µst
SU;STO, Set-up Time for STOP Condition
Fast Mode
0.6
µs
High-Speed Mode
160
ns
t9
Standard Mode
-
1000
ns
tRDA, Rise time of SDA signal
Fast Mode
20 + 0.1CB 300
ns
High-Speed Mode, CB = 100pF max 10
80
ns
High-Speed Mode, CB = 400pF max 20
160
ns
t10
Standard Mode
-
300
ns
tFDA, Fall time of SDA signal
Fast Mode
20 + 0.1CB 300
ns
High-Speed Mode, CB = 100pF max 10
80
ns
High-Speed Mode, CB = 400pF max 20
160
ns
t11
Standard Mode
-
1000
ns
tRCL, Rise time of SCL signal
Fast Mode
20 + 0.1CB 300
ns
High-Speed Mode, CB = 100pF max 10
40
ns
High-Speed Mode, CB = 400pF max 20
80
ns
t11A
Standard Mode
-
1000
ns
tRCL1, Rise time of SCL signal after a re-
Fast Mode
20 + 0.1CB 300
ns
peated START Condition and after an
High-Speed Mode, CB = 100pF max 10
80
ns
Acknowledge bit.
High-Speed Mode, CB = 400pF max 20
160
ns
t12
Standard Mode
-
300
ns
tFCL, Fall Time of SCL signal
Fast Mode
20 + 0.1CB 300
ns
High-Speed Mode, CB = 100pF max 10
40
ns
High-Speed Mode, CB = 400pF max 20
80
ns
tSP
4
Fast Mode
0
50
ns
Pulsewidth of Spike Suppressed.
High-Speed Mode
0
10
ns
tPOWER-UP
1
µs
Power-up Time
I
2C TIMING SPECIFICATIONS1(Continued.)
NOTES
1See Figure 1. C
B refers
to the capacitance load on the bus line. Hs-Mode timing specifications apply to the AD7994-1/AD7993-1 only. Stan-
dard and Fast Mode timing specifications apply to both the AD7994-0/AD7993-0 and the AD7994-1/AD7993-1.
2The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a nega-
tive effect on EMC behavior of the part.
4Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50ns or 10ns for Fast Mode or High-Speed mode
respectivley.
Specifications subject to change without notice.



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