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AD7994/AD7993

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PRELIMINARYTECHNICAL DATA

Table XIb. Alert Status Register Bit Function

Description

Bit Mnemonic Comment

D 0 CH1LO

Violation of DATALOW limit on Channel

1 if this bit set to 1, no violation if 0.

D 1 CH1HI

Violation of DATAHIGH limit on Chan

nel 1 if this bit set to 1, no violation if 0.

D 2 CH2LO

Violation of DATALOW limit on Channel

2 if this bit set to 1, no violation if 0.

D 3 CH2HI

Violation of DATAHIGH limit on Chan

nel 2 if this bit set to 1, no violation if 0.

D 4 CH3LO

Violation of DATALOW limit on Channel

3 if this bit set to 1, no violation if 0.

D 5 CH3HI

Violation of DATAHIGH limit on Chan

nel 3 if this bit set to 1, no violation if 0.

max conversion results, the Alert_Flag bit, D15, can be

used to indicate that an alert has happened on another one

of the Input channels.

It must be noted that on power-up, the contents of the

DATAHIGH register for each channel will be fullscale,

while the contents of the DATALOW registers will be

zeroscale, by default minimum and maximum conversion

values being stored in this way will be lost if power is

removed or cycled.

When using the limit registers to store the min and max

conversion results, the Alert_Flag bit, D15, is used to

indicate that an alert has happened on another one of the

Input channels. If the Alert_Flag bit is set to 1, it will be

reset when the Conversion result returns to a value at least

N LSBs above the DATALOW Register value or below the

DATALOW Register value or if bits D2 and D1 of the

Configuration Register are set to 1. The Alert_Flag bit in

the limit registers is useful if the user is not reading from

the conversion result register when reading the min and

max conversion results from the limit registers.

ALERT STATUS REGISTER

The Alert Status Register is a 8-bit read/write register,

which provides information on an Alert event. If a conver-

sion results in activating the ALERT pin or the Alert_Flag

bit in the Conversion Result Register, as described in the

Limit Registers section, then the Alert Status Register may

be read to gain further information. It contains 2 status

bits per channel, one corresponding to the DATAHIGH

limit and the other to the DATALOW limit. Whichever bit

has a status of 1 will show where the violation occured, i.e.

on which channel and whether on upper or lower limit. If

a second alert event occurs on the other channel between

receiving the first alert and interrogating the Alert Status

be set also.

The entire contents of the Alert Status register may be

cleared by writing 1,1, to bits D2 and D1 in the Configu-

ration register as shown in Table VI. This may also be

acheived by ‘writing’ all 1’s to the Alert Status Register

itself. This means that if the Alert Status Register is ad-

dressed for a write operation which is all 1’s, then the

contents of the Alert Status Register will then be cleared

or resest to all 0’s. Alternatively, an individual active Alert

bit(s) may be reset within the Alert Status Register by

performing a write of ‘1’ to that bit alone. The advantage

of this is that once an Alert event has been serviced, that

particular bit can be reset, e.g. CH1LO, without clearing

the entire contents of the Alert Status Register, thus pre-

serving the status of any additional Alert, e.g. CH2HI,

which may have occured while servicing the first. If it is

not necessary to clear an Alert directly after servicing then

obviously the Alert Status register may be read again im-

mediately to look for any new Alerts, bearing in mind that

the one just serviced will still be active.

Table XIa. Alert Status Register

CH4HI CH4LO CH3HI CH3LOCH2HI CH2LOCH1HI CH1LO

D 6 CH4LO

Violation of DATALOW limit on Channel

4 if this bit set to 1, no violation if 0.

D 7 CH4HI

Violation of DATAHIGH limit on Chan

nel 4 if this bit set to 1, no violation if 0.

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