MC9328MX1 datasheet(88/96 Pages) FREESCALE

88 / 96 page

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor

Specifications

3.22 CMOS Sensor Interface

The CSI module consists of a control register to configure the interface timing, a control register for statistic data

generation, a status register, interface logic, a 32

× 32 image data receive FIFO, and a 16 × 32 statistic data FIFO.

3.22.1 Gated Clock Mode

Figure 68 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the

CSI is programmed to received data on the positive edge. Figure 69 on page 89 shows the timing diagram when the

CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative

edge. The parameters for the timing diagrams are listed in Table 42 on page 89.

STCK high to STXD high impedance

17.90

29.75

15.7

26.1

SRXD setup time before SRCK low

1.14

–

1.0

–

SRXD hole time after SRCK low

–

Synchronous Internal Clock Operation (Port B Alternate Function)2

SRXD setup before STCK falling

18.81

–

16.5

–

SRXD hold after STCK falling

–

Synchronous External Clock Operation (Port B Alternate Function)2

SRXD setup before STCK falling

1.14

–

1.0

–

SRXD hold after STCK falling

–

All the timings for both SSI modules are given for a non-inverted serial clock polarity (TSCKP/RSCKP =

0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync

STFS/SRFS shown in the tables and in the figures.

There is one set of I/O signals for the SSI2 module. They are from Port C alternate function (PC19 –

PC24). When SSI signals are configured as outputs, they can be viewed at Port C alternate function a.

When SSI signals are configured as inputs, the SSI module selects the input based on FMCR register bits

in the Clock controller module (CRM). By default, the input is selected from Port C alternate function.

bl = bit length; wl = word length

Table 41. SSI 2 Timing Parameter Table (Continued)

Ref

No.

Parameter

1.8V +/- 0.10V

3.0V +/- 0.30V

Unit

Minimum

Maximum

Minimum

Maximum

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