MC9328MX1 datasheet(25/96 Pages) FREESCALE

Nome de Peças	MC9328MX1

Descrição Electrónicos	i.MX Integrated Portable System Processor

PDF	96 Pages

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Fabricante Electrônico	FREESCALE [Freescale Semiconductor, Inc]

Página de início	http://www.freescale.com

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Specifications

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor

3.9.2.2 DTACK Read Cycle DMA Enabled

Figure 7. DTACK Read Cycle DMA Enabled

DTACK asserted to OE negated

3T+2.2

4T+6.86

Data hold timing after OE negated

–

Data ready after DTACK asserted

OE negated to CS negated

0.5T+0.24

0.5T+0.67

OE negated after EB negated

0.5

1.5

DTACK pulse width

Note:

0. DTACK assert means DTACK become low level.

1. T is the system clock period. (For 96MHz system clock)

2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur

only when EBC bit in CS5L register is clear.

3. Address becomes valid and CS asserts at the start of read access cycle.

4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.

Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)

Number

Characteristic

(3.0 ± 0.3) V

Unit

Minimum

Maximum

DTACK

Address

CS5

(logic high)

Databus

programmable

min 0ns

(1)

(6)

(7)

(3)

(4)

(2)

(5)

(8)

(input to MX1)

(9)

(10)

(11)

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