MC9328MX1 datasheet(63/96 Pages) FREESCALE

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Specifications

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor

Table 28. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table

Symbol

Description

Minimum

Corresponding Register Value

Unit

End of OE to beginning of VSYN

T5+T6

+T7+T9

(VWAIT1·T2)+T5+T6+T7+T9

HSYN period

XMAX+5

XMAX+T5+T6+T7+T9+T10

VSYN pulse width

VWIDTH·(T2)

End of VSYN to beginning of OE

VWAIT2·(T2)

HSYN pulse width

HWIDTH+1

End of HSYN to beginning to T9

HWAIT2+1

End of OE to beginning of HSYN

HWAIT1+1

SCLK to valid LD data

-3

End of HSYN idle2 to VSYN edge

(for non-display region)

End of HSYN idle2 to VSYN edge

(for Display region)

T10

VSYN to OE active (Sharp = 0),

when VWAIT2 = 0

T10

VSYN to OE active (Sharp = 1),

when VWAIT2 = 0

Note:

•

Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.

•

VSYN, HSYN and OE can be programmed as active high or active low. In Figure 46, all 3 signals are active low.

•

The polarity of SCLK and LD[15:0] can also be programmed.

•

SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 46, SCLK is

always active.

•

For T9 non-display region, VSYN is non-active. It is used as an reference.

•

XMAX is defined in pixels.

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