MC9328MX1 datasheet(28/96 Pages) FREESCALE

28 / 96 page

MC9328MX1 Advance Information, Rev. 4

Freescale Semiconductor

Specifications

3.9.2.4 DTACK Write Cycle DMA Enabled

Figure 9. DTACK Write Cycle DMA Enabled

Note:

0. DTACK assert mean DTACK become low.

1. T is the system clock period. (For 96MHz system clock)

2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register.

3. Address becomes valid and RW asserts at the start of write access cycle.

4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.

Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz

Number

Characteristic

(3.0 ± 0.3) V

Unit

Minimum

Maximum

CS5 assertion time

See note 2

–

2EB assertion time

See note 2

–

3CS5 pulse width

–

4RW negated before CS5 is negated

1.5T+0.58

1.5T+1.58

Address inactive before CS negated

–

0.93

DTACK asserted after CS5 asserted

–

1019T

Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)

Number

Characteristic

(3.0 ± 0.3) V

Unit

Minimum

Maximum

DTACK

Address

CS5

(logic high)

Databus

programmable

min 0ns

programmable

min 0ns

(1)

(2)

(7)

(8)

(4)

(5)

(3)

(6)

(9)

(output from MX1)

(10)

(11)

(12)

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