A6985F datasheet(47/77 Pages) STMICROELECTRONICS

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A6985F

Application notes

The CDELAY is dimensioned accordingly with Equation 42:

Equation 42

The maximum suggested capacitor value is 270 nF.

7.5

Synchronization (LNM)

Beating frequency noise is an issue when multiple switching regulators populate the same

application board. The A6985F synchronization circuitry features the same switching

frequency for a set of regulators simply connecting their SYNCH pin together, so preventing

beating noise. The master device provides the synchronization signal to the others since the

SYNCH pin is I/O able to deliver or recognize a frequency signal.

For proper synchronization of multiple regulators, all of them have to be configured with the

same switching frequency (see Table 6 on page 11), so the same resistor connected at the

FSW pin.

In order to minimize the RMS current flowing through the input filter, the A6985F device

provides a phase shift of 180° between the master and the SLAVES. If more than two

devices are synchronized, all slaves will have a common 180° phase shift with respect to

the master.

Considering two synchronized A6985F which regulates the same output voltage (i.e.:

operating with the same duty cycle), the input filter RMS current is optimized and is

calculated as:

Equation 43

The graphical representation of the input RMS current of the input filter in the case of two

devices with 0° phase shift (synchronized to an external signal) or 180° phase shift

(synchronized connecting their SYNCH pins) regulating the same output voltage is provided

in Figure 34. To dimension the proper input capacitor please refer to Section 7.6.1: Input

capacitor selection on page 52.

CDELAY

ISSCH TDELAY



VDELAY

------------------------------------------

AT

DELAY



1.234V

-------------------------------------

IRMS

IOUT

------------

1 2D

–





if D < 0.5



IOUT

------------

2D 1

–

 22D

–





if D > 0.5













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