A6985F datasheet(46/77 Pages) STMICROELECTRONICS

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Application notes

A6985F

46/77

DocID027738 Rev 2

7.3

MLF pin

A resistor connected to the MLF pin features the selection of the between low noise mode /

low consumption mode and the different RST thresholds. The pinstrapping is performed at

power-up, before the soft-start takes place. The FSW pin is pinstrapped and then driven

floating in order to minimize the quiescent current from VIN.

Please refer to Table 7 on page 11, Table 8, and Table 9 on page 12 to identify the pull-up /

pull-down resistor value. (LNM, RST threshold 93%) / (LCM, RST threshold 93%) preferred

codifications don't require any external resistor.

7.4

Voltage supervisor

The embedded voltage supervisor (composed of the RST and the DELAY pins) monitors the

regulated output voltage and keeps the RST open collector output in low impedance as long

as the VOUT is out of regulation. In order to ensure a proper reset of digital devices with

a valid power supply, the device can delay the RST assertion with a programmable time.

Figure 33. Voltage supervisor operation

The comparator monitoring the FB voltage has four different programmable thresholds

(80%, 87%, 93%, 96% nominal output voltage) for high flexibility (see Section 7.3: MLF pin,

Table 7 on page 11, Table 8, and Table 9 on page 12).

When the RST comparator detects the output voltage is in regulation, a 2

A internal current

source starts to charge an external capacitor to implement a voltage ramp on the DELAY

pin. The RST open collector is then released as soon as VDELAY = 1.234 V (see Figure 33).

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