SPEAR1310 datasheet(50/57 Pages) STMICROELECTRONICS

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Direct memory access controller (DMAC)

SPEAr1310

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Doc ID 17528 Rev 4

Direct memory access controller (DMAC)

The DMAC is an AHB-central DMA controller core that transfers data from a source

peripheral to a destination peripheral over two AHB buses. A wrapper is designed to

instantiate 2 DMAC cores (each with 2 AHB master interfaces), 2 ICMs (which arbitrate the

same master interface of each DMAC) and a MUX (which manages multiple peripheral

handshaking interfaces).

34.1

Main features

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AMBA 2.0-compliant

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AHB slave interface – used to program the DMAC

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8 channels, one per source and destination pair

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Unidirectional channels – data transfers in one direction only

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Programmable channel priority

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2 independent AHB master interfaces

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Data bus width configured to 64 bits for each AHB master interface

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Configurable endianness for master interfaces

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Support for memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral DMA transfers

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Component ID parameters for configurable software driver support

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Programmable source and destination addresses (on AHB bus)

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Address increment, decrement or no change

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Multiblock transfers achieved through linked lists (block chaining)

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Independent source and destination selection of multiblock transfer type

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Scatter/Gather

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Single FIFO per channel for source and destination

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FIFO depth configured to 16 bytes for the first 4 channels and to 128 bytes for the last 4

channels

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D flip-flop-based FIFO

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Automatic data packing or unpacking to fit FIFO width

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Programmable source and destination for each channel

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Programmable transfer type for each channel (memory-to-memory, memory-to-

peripheral, peripheral-to-memory, and peripheral-to-peripheral)

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Programmable burst transaction size for each channel

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Programmable enable and disable of DMA channel

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Support for disabling channel without data loss

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Support for suspension of DMA operation

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Support for RETRY, SPLIT, and ERROR responses

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