SPEAR1310 datasheet(20/57 Pages) STMICROELECTRONICS

Nome de Peças	SPEAR1310

Descrição Electrónicos	Dual-core Cortex A9 embedded MPU for communications

PDF	57 Pages

Scroll/Zoom	100%

Fabricante Electrônico	STMICROELECTRONICS [STMicroelectronics]

Página de início	http://www.st.com

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Serial memory interface (SMI)

SPEAr1310

20/57

Doc ID 17528 Rev 4

Serial memory interface (SMI)

The serial memory interface integrated in SPEAr1310 acts as an AHB slave interface (32,

16- or 8-bit) to SPI-compatible off-chip memories. SMI allows the CPU to use these serial

memories either as data storage or for code execution.

11.1

Main features

●

Supports a group of SPI-compatible Flash and EEPROM devices

●

Acts always as a SPI master and up to 4 SPI slave memory devices are supported

(through as many chip select signals), with up to 16 MB address space each; 2 out of

the 4 chip select are available on PL_GPIOs.

●

The SMI clock signal (smi_clk_o) is generated by SMI (and input to all slaves) using

clock provided by the AHB bus

●

smi_clk_o can be up to 50 MHz in fast read mode (or 20 MHz in normal mode), and it

can be controlled by a programmable 7-bit prescaler allowing 127 different clock

frequencies.

SPEAR1310 Folha de dados(PDF) 20 Page - STMicroelectronics