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SPEAr1310

Universal asynchronous receiver/transmitter (UART)

Doc ID 17528 Rev 4

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Universal asynchronous receiver/transmitter (UART)

A UART is responsible for performing the main task in serial communications with

computers. The device changes incoming parallel information to serial data that can be sent

on a communication line. The UART performs all the tasks, timing, parity checking, etc.

needed for the communication.

The UART is an APB module in the power bus subsystem; it supports standard

asynchronous communication bits (start, stop and parity), which are added prior to

transmission and removed on reception.

The UART can support serial data baud rate, dc up to UARTCLK_max_freq/16. It supports

modem control functions CTS, DCD, DSR, RTS, DTR and RI.

23.1

Main features

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Separate 16x8 transmit and 16x12 receive first-in, first-out memory buffers (FIFOs)

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Programmable FIFO disabling for 1-byte depth

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Programmable baud rate generator

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Independent masking of transmit FIFO, receive FIFO, receive timeout, modem status,

and error condition interrupts

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Support for direct memory access (DMA)

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False start bit detection

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Line break generation and detection

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Programmable hardware flow control

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Fully-programmable serial interface characteristics:

–

data can be 5, 6, 7, or 8 bits

–

even, odd, stick, or no-parity bit generation and detection

–

1 or 2 stop bit generation

The following key parameters are programmable:

●

Communication baud rate, integer, and fractional parts

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Number of data bits

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Number of stop bits

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Parity mode

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FIFO enable (16 deep) or disable (1 deep)

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FIFO trigger levels selectable between 1/8, 1/4, 1/2, 3/4, and 7/8

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Hardware flow control

●

The UART clock can be fixed at 48 MHz or can be programmed using the

miscellaneous register UART_CLK_SYNT.

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