SPEAR1310 datasheet(35/57 Pages) STMICROELECTRONICS

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SPEAr1310

RS485 HDLC controller

Doc ID 17528 Rev 4

35/57

RS485 HDLC controller

21.1

Main features

The main features of the RS485 HDLC controllers are:

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AMBA 2.0 compliant

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AMBA slave interface, used to program RS485/HDLC

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AMBA master interface, used to transfer data between DDR and IP

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DMA engine included to alleviate CPU from transferring data

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Data buffer queue making bulk data transfer more efficient

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Interrupt Queue supplying more interrupt information

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Miscellaneous Interrupt generation

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Frame transmitted/received

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End of data buffer queue

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Buffer empty/ buffer filled

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Tx/Rx DMA FIFO underflow/overflow

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Interrupt queue overflow

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Interrupt FIFO overflow

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Abort generation and detection

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Oversize and non-octet-aligned frame detection

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CRC and alignment error generation

RS485 interface main features:

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Five signals for each RS485 interface

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Duplex Tx/Rx communication

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Maximum Tx/Rx data rate 3.88 Mbps

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Collision detection and automatic frame re-transmition

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Data sending/sampling timing configurable

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Tx data can be sent out after the rising/falling edge of Tx clock

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Rx data are sampling at the rising/falling edge of Rx clock

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No constraints on clock duty cycle, data sending/receiving only depends on the

rising/falling edge of Tx/Rx clock

HDLC controller main features:

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Compliant with ISO/IEC13239

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Standard HDLC frame code/decode

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