SLx 24C01/02/P

Semiconductor Group

21

1998-07-27

The control byte CTx is followed by 8 parameter bytes identical to the 8 data bytes of the

page to be protected or unprotected. The data of the first entered byte must be identical

to the data byte stored at the lowest address of the current page. The other 7 bytes have

to be identical to the bytes stored in ascending address order within the same page.

A successful verification of each byte is indicated by the EEPROM by pulling the SDA

line to low (acknowledge ACK).

After verification of the last byte, the bit programming procedure is initiated by the STOP

condition. Programming is started only if all 128 bits of a page have been verified

successfully. If bit programming has taken place, the address counter points to the

uppermost address of the respective page. The write or erase cycle is finished latest

after 4 ms. Acknowledge polling may be used for speed enhancement in order to

indicate the end of the write or erase cycle (refer to chapter 5.3 Acknowledge Polling).